SU625209A1 - Electric circuit testing arrangement - Google Patents

Description

The invention relates to automation and computing and can be used to control electrical circuits in electro-automatic systems.

Devices for controlling electrical circuits are known that contain a mismatch of the checked and reference circuits, a group of control keys, a generator of clock-operated pulses, a pulse counter, a decrypter of the circuit number, and a control trigger. The disadvantages of these devices are narrow functionality that does not provide deep (th automation of electrical circuit testing).

The closest in essence to technical solutions proposed is a device for automatically finding faults in circuit diagrams containing a reference object connected by an input to the first output of the control unit, and an output to the first input of a mismatch element, the second input of which is connected to the input of the device, the output element the mismatch is connected to the first input of the first element AND, the output of which is connected to the first input of the element OR, the second input of the first element AND is connected through a censor to the output of the counter ika, the counting input of which is connected to the output of the second element I, whose inputs are connected respectively to the output of the clock generator, the input of the control unit, the output of the trigger 2.

A disadvantage of the known device is the low speed due to the numerous manual operations and the need to interrogate obviously good

chains.

The purpose of the invention is to increase the speed of the device.

Claims (2)

This is achieved by introducing two AND elements, a fault register and a delay element into the device, with the second output of the control unit and the output of the mismatch element respectively connected to the inputs of the third AND element connected by the output to the second input of the OR element whose output 3625 is connected through the delay element with the first input of the trigger and the first input of the fourth element I, connected by the output to the input of the fault register, the output of the higher bit of the counter is connected to the second output of the trigger, the output of which oedinen to a second input of the fourth AND gate, the output of the counter is connected to address input of register malfunctions. The drawing is a structural electrical circuit diagram of the device. It contains a mismatch element 1 scanned 2 and a reference 3 objects, elements 4 and 5, element 6 or 6, delay element 7, trigger 8, 9 clock pulses, pulse 1 element, C4eT4HKill pulses, device input 12, decoder 13, control unit 14, element 15 and fault register 16. The device works as follows. When a signal is applied, the measurement from the control unit 14 to the input of the elements 4 is carried out a simultaneous interrogation of the status of all the channels of the multi-garden mismatch circuit 1. In the event of at least one malfunction, trigger 8 through element OR 6i delay element 5 5 is set to one and, thus, a series of polling signals from generator 9 will be fed to the inputs of element 5 via element I Yu, counter 11 and decoder 13. The position of the trigger does not change until the end of the polling of the quads, after which, when the counter overflows, the signal from the high-order trigger output sets trigger 8 to the zero position. To memorize the addresses of faulty channels, the signals from the output of the OR element bis bis output of the counter 11 are transferred to the register of 16 faults. 14, the control signal is issued to connect the next reference circuit and the signal is measured. Thus, the device allows to increase the speed of control of electrical circuits. The invention The device for checking electrical circuits, containing a reference object connected to the first output of the control unit and the output to the first input of a mismatch element, the second input of which is connected to the device input, the output of the mismatch element connected to the first input of the first And element, the output of which connected to the first input of the OR element, the second input of the first element AND is connected via a decoder to the output of the account “scale, the counting input of which is connected to the output of the second element AND, the inputs of which are These values correspond respectively to the output of the clock generator, the input of the control unit, the output of the trigger, characterized in that, in order to increase the speed of the device, two AND elements, a fault register and a delay element are entered into it, the second output of the control unit and the output of the mismatch element are connected respectively with the inputs of the third element And connected by the output to the second input of the element OR, the output of which is connected through the delay element to the first input of the trigger and the first input of the fourth element AND, The output of the fault register is input, the high-order counter is connected to the second trigger output, the output of which is amply connected to the second input of the fourth And element, and the counter is connected to the address input of the fault register. Sources of information taken into account in the examination: 1. Authors ssshechelstvo USSR № 220639, CL 06 F 15/46, 1966. 2.ABTOpckoe certificate of the USSR No. 238236, cl. Q About R 15/46, 1967.