SU621086A2 - Voltage-to-digital code converter - Google Patents

Description

The invention relates to data conversion and transmission devices and can be used in information measurement technology.

A known voltage converter is a digital code according to the author. St. No. 195209, in which, in order to reduce the use of energy in the measurement information, only those samples are taken that lie in the non-linear portions of the signal being converted. The known converter contains a comparison circuit, a pulse generator, a reversible counter, a kotz-voltage converter, a memory device, a frequency divider and a comparison circuit, the reversible counter being connected to the memory device, and the frequency divider connected to the memory device through the gates l.

A disadvantage of the known transducer is the complexity of the comparison scheme for time intervals, due to the presence of significant dynamic error measurements, the difficulty of reconfiguration and the substantial conversion error at the extremums of the input signal.

The purpose of the invention is to improve the accuracy of the analog signal, simplify the converter circuit, increase the dynamic range of the input signal, simplify the converter retune and ensure subsequent control of the accuracy of the conversion.

This is achieved by the fact that in the converter according to auth.st. J 195209. unit, the comparison of time intervals is made in the form of a counter, a register and an analyzer block. In the register state, the control input of the counter is connected via a trigger and a switch with parallel transfer circuits of the reversible counter, the counter input of the counter is connected to a pulse generator, and the trigger the counter is connected to the counting inputs of the register, and the output buses of the analysis block are combined with the output of the trigger for fixing the extrema and connected to the .prohibition inputs of the output keys.

Introduction these. elements allows to reduce to MHHHMjTviy the dynamic measurement error specified by A U and thereby ensure that the operation of comparing two binary numbers on one register instead of the topicalists is performed.

The drawing shows a pattern; a cturn circuit of a converter containing a block

1 comparing time intervals and block 2 fixing extrema.

The Converter operates as follows.

. A null-organ 3 simultaneously receives an input signal and a compensation signal from a 4-digit code-voltage converter, Depending on the ratio of these signals using keys 5, and 6: or one of the inputs (addition or subtraction) of the reversible counter 7 is opened (if one of the signals; it exceeds the other), or both inputs are closed (if both signals are equal within the limits of the null-organ sensitivity)

In the nepfeuM case, clock pulses (from generator 8 are fed to reversible counter 7, in the second case they are not received-.

This provides the following pemmjf. conversion, with the result that the counter 7 is always the digital equivalent of the signal to be converted. The digital value can be read out at any time by strobing the output keys 9.

The formation of a reference signal (pulse line) is carried out by the comparing unit 1. spacing and block

2 fixations of extrema.

Block 1 of comparison of time internals consists of a short-circuit of counter 1O, block 11 of keys, register 12 and block 13 of the analyzer for: I controls the operation I of counter 1O with key 14 and trigger 15. At one trigger input 15, signals are received from switch 16 to another - from line 17 delay. The time intervals corresponding to the time of changing the input signal by a given value of D U increments are formed by a noi transfer pulse of the reversible counter 7, i.e. the value of D U determines em ... with a strictly defined number of pulses of the clock generator arriving at the input of the counter 7. The selection of this number is made by the switch 16

When a next pulse arrives at the trigger 15 from the switch 16, the trigger 15 closes the key 14. On the counter 10, a code is recorded corresponding to the measured time interval. The signal from the other arm of the trigger through the time determined by the delay line 18 forms the signal. The overwrite, which opens the key block 11, and the code from the counter 10 enters the counting inputs of the register 12 triggers.

In register 12., the code stored in this register and corresponding to the previous measurement is compared with the code from the counter and corresponding to the current measurement. Depending on the ratio of these codes, block 13 of the sipnal analysis analysis resolution. - generates No Zero or Zero signals. The first one means; what needs to be done is the counting, and it comes first to the formation of this signal, the Countdown, and then to the training circuit of the comparison unit 1 to a transition state. Signal There are zero immediately enters the circuit preparation. This circuit consists of delay lines 17-21, which further ensure the operation of the entire circuit in the following sequence: blanking register 12, rewriting the code from counter 10B, register 12 for storage until the next comparison, blanking counter 10, setting trigger 15 to its original state (line 17 delay). The input of the extrema is captured by the fixation trigger 22 by the extremum, the inputs of which are connected to the subtraction and addition channels. The transition of the counter 7 from the subtraction mode to the addition mode (or vice versa) indicates that the signal has passed an extremum. Triger changes its state. This is fixed by a differentiating chain 23, the signal from which is fed to the formation of a reference pulse.

Thus, the transducer selects all those samples that lie on the nonlinear parts of the signal, including the extremum.

Claims (1)

Invention Formula . Converter auth. St. No. 1952О9, characterized in that, in order to increase the accuracy of the input signal, simplify the converter and improve its performance, the time interval comparison unit is designed as a counter, register, and state analysis block, and the control input of the counter is connected through a trigger and a switch with chains of parallel transfer of a reversible counter, the counter input of the counter is connected to a pulse generator, the trigger of the counter with the counting inputs of the register, and the output buses of the analysis unit bvdineky yield trigger locking extrema and are connected to inputs of prohibiting output keys. 6210 66 Sources of information taken into account during the examination: 1. USSR Copyright Certificate No. 195209, cl. H 03 K 13/17, 06.06.66.