SU563679A1 - Integrator - Google Patents

Description

Sources 15, 16, and 17 are TTL valves.

The integrator works as follows.

The transistors 3 and 4 form a current switch controlled by the source 17. If the output of the source 17 is logical 1, then the transistor 3 is open and the transistor 4 is closed. A logical "O at the output of the source 17 closes the transistor 3 and opens the transistor 4. The constant current / generated by the controlled generator 12 charges the capacitor 9 or the capacitor 10, respectively. However, the charge of the capacitors is possible only when the source 15 is in the state of the logical "O, and the source 16 - in the state of" 1.

Consider the case when the information sequence at the output of source 17 has the form 11111 ... In this case, the current / constant flows through transistor 3.

During half the clock frequency period, the source 15 is in the state "1 and the capacitor 9 is discharged along the circuit: the source 15, the diode 7, the diode 5 and the storage capacitor P. The charge of the capacitor 9 begins with the current / (the diode 7 is closed).

ZAR D QA, obtained by capacitor 9, rat

veins QA A, where (the duration of the negative pulse at the output of the source 15), and, therefore, e depends on the amplitude of the control pulses. In the next cycle, the accumulated charge QA is distributed between the capacitors 9 and I and the voltage increases to С / - by the magnitude of the quantization step.

C + QA

one

C, + C,

C, +

in the real scheme the relation is fulfilled, therefore

G,.

i

Consider now the case when the output of the source 17 is constantly supported by the logical "O. During half the clock frequency period, the capacitor 10 is discharged along the circuit: source 16, transistor 2, storage capacitor 11. At this time, diode 6 is closed, diode 8 is open, and current / flows through source 15.

In the second half of the clock period, the diode 8 is closed, the diode 6 is open, and the capacitor 10 is charged with current / circuit: source 16, diode 6, transistor 4, controlled oscillator 12.

ZAR d QB obtained by the capacitor 9 is equal to

Q, t. /

and also does not depend on the amplitude of the control pulses.

In the next clock cycle, transfer of the charge QB to the capacitor 11 occurs, and the voltage at C / decreases by one quantization level.

.

i

Thus, depending on the information signal at the output of the source 17, the output voltage of the integrator changes accordingly either by -G or + G every clock cycle.

Claims (1)

Invention Formula The integrator containing information and clock sources, the first transistor, whose base is connected to the storage capacitor and cathode of the first diode, and the emitter to the anode of the first diode and one of the plates of the first metering capacitor, the second transistor, whose collector is connected to the storage capacitor, and emitter - with the anode of the second diode and with one of the plates of the second metering capacitor, and a power source, characterized in that, in order to expand integrator functionality, additional diodes are introduced, a controlled current generator, a source of negative voltage and additional transistors, the emitters of which are connected to the output of a controlled current generator, the base of the first additional transistor is connected to the source of information pulses, and the collector is connected to the cathode of the first additional the diode, the base of the second additional transistor is connected to the source of the reference voltage, the collector is connected to the cathodes of the second diode and the second additional diode, the anodes of the additional diodes are connected to the source of clock pulses, the cathode of the first additional diode - to the other plate of the first metering capacitor, and the other plate of the second metering capacitor is connected to the source of inverted clock pulses.