SU558400A1 - Voltage level conversion device - Google Patents

Description

one

The invention relates to the field of electronics, in particular, to a pulse technique and is intended for use in integrated digital circuits.

A device for converting voltage levels is known, which is a common key cascade on complementary MOSFETs with a high ratio of specific steepness of switching and load transistors.

Such a key stage in one of the logical states consumes significant power.

A device for converting voltage levels is known, which contains two complex inverters on complementary MDPtransistors, in which the sources of the switching transistors of the first and second complex inverters are connected to the zero potential bus, the gates to the forward and inverse inputs, and the outlets to the inverse and direct outputs respectively, the sources of the load transistors of the first and second complex inverters are connected to the power bus, the gates to the direct and inverse outputs, and the drain to the inverse and direct outputs of the circuit correspond to venno.

The disadvantage of this device is the conversion of voltage levels is narrow

field of application and low speed.

The aim of the invention is to enhance the functionality and increase the Silence of the voltage conversion circuit.

To do this, a voltage conversion device containing two inverters per

MIS transistors, with the source of the switching transistor of the first inverter connected to the zero potential bus, the gate to the input bus, and the drain to the gate of the load transistor of the second inverter,

the drain of the switching transistor of the second inverter - with the gate of the load transistor of the first inverter and the drain of the load transistor of the second inverter; the sources of the load transistors are connected to

bus, introduced an additional load transistor, the drain of which is connected to the drain of the switching transistor of the first inverter, the source to the drain of the load transistor of the first inverter, and the gate

the input bus, in addition, the source of the switching transistor of the second inverter is connected to the input bus, and the gate to the additional bus iitani. The drawing shows the schematic diagram of the proposed device.

The device contains a load transistors 1, 2; switching transistors 3, 4; additional load transistor 5; input bus 6; inverse and direct outputs 7, 8, respectively; bus 9 - power supply; bus 10 zero potential; idiu 11 supplementary power source.

Transistors 1, 3 form the first inverter, and transistors 2, 4 form the second inverter.

The device works in the following way.

Suppose, in the initial state, the level on the input bus 6 of the device corresponds to a logical "O. At the same time, transistors 2 and 3 are closed, transistors 1, 4 and 5 are open, and the levels of direct and inverse outputs 8, 7 correspond to "O and" 1, respectively, and the logic level "1 at output 7 is equal to the voltage of bus 9 of power supply .

When the logic level at the output changes from "O to" 1, the value of which is less than the voltage of the power supply bus 9, the switching transistor 3 opens, the conductivity of the additional load transistor 5 decreases, and the switching transistor 4 closes on the source and the voltage and output 8 is increased to the voltage of unlocking transistor 4 across the source equal to

p and

nd About

and

1 +

where is the dc voltage on the bus 10 of the additional power source, while reducing the conductivity of the transistor 1.

Open transistors 1, 3 and 5 form a divider. The output voltage 7 begins to change from a logical "1 to a level determined by the ratio of the sizes (specific steepness) of these transistors. At some point in time, the transistor 2 opens and the voltage at output 8 begins to increase to the value of the voltage of the source bus 9

And 11thany. The transistor 1 closes in this way and the output voltage 7 is reduced to "O." In the new state, transistors 1 and 4 are closed, and transistors 2, 3, and 5 are open,

the levels of both direct and inverse outputs 8, 7 correspond to “1 and“ О, respectively.

The device is reset to its original state in the same way. First, the transistor 3 is locked and the transistor 4 is unlocked. The open transistors 2 and 4 form a divider, resulting in a voltage change at the output of 8c "1 to" O leads to the opening of the transistor 1 and changing the voltage at the output 7 with "O

at “1.

F o rmly inventions

A device for converting voltage levels, containing two inverters for additional MOS-frequency transistors, with the source switching; its first inverter transistor is connected to the zero voltage bus, the gate to the input bus, and the drain to the load transistor of the second inverter, the drain of the second transistor of the second inverter with gate with load transistor of the first inverter

and the drain of the load transistor of the second inverter, the sources of the load transistors connected to the power bus, are different in that in order to expand the functionality and increase the speed, an additional load transistor is introduced into it, the drain of which switches to the drain of the switching transistor of the first inverter, the source to the drain the load transistor of the first inverter, and the gate - to the input bus, in addition, the source of the switching transistor of the second inverter and the keys to the input spy, and the gate - to the downstream Flax shiie power.