SU530268A1 - Digital phase meter - Google Patents

Description

The circuit of the invention is to increase the speed and accuracy of measuring phase shifts. The delivered circuit is achieved by the fact that a phase meter containing input for measuring and on-channel channels associated with a time trigger, synchronous meters for the measuring and reference channels, a clock generator connected to the counters, and an arithmetic unit connected to the two ear meter of both channels, and including a phase difference calculator, an adder, and a long-term memory block, reset and block write shapers, a rewrite and compute command signal shaper are entered phase differences and a sync pulse generator of the output code recording, as well as operating memory blocks, with their inputs connected to the outputs of synchronous counters of the corresponding channels, control input — to the output of the sigpap generator of the rewriting command, and outputs — to the input of the phase difference calculator, when In this case, each of the drivers of the reset and write blocking signals is connected to the output of the clock generator by one of its own inputs, the other input is connected to the output of the input driver of the corresponding channel, and outputs - to the control inputs of synchronous counters, the signal generator of the overwrite command and phase difference calculation by one of the inputs is connected with the clock pulse output, the other inputs are connected to the outputs of the reset and blocking signal drivers, as well as the trigger source, the sync pulse generator output code one of the inputs is connected to the output of the clock, and the other with the signal channel Start, while the output of the time trigger is connected to the control input of the block nnoy. The drawing shows a structurally electronic phase meter circuit. The digital phase meter contains input forks 1 and 2 of the reference and measuring channels, time 3, synchronous counters 4 and 5 of the reference and measuring channels, a generator 6 of clock pulses and an arithmetic unit 7, B1, a difference calculator block 8, an adder 9 and block 10 long-term memory. In addition, the formers 11 and 12 of the reset and write blocking signals, the shaper 13 of the command for rewriting and calculating the phase difference, the blocks 14 and 15 of the working memory, and the shaper 16 of the write code of the output code in the register device are entered into the phase meter. The phase meter also contains the start signal input 17, the inputs 18 and 19 of the measuring and reference channels, the output 20 of the code of the measured phase shifts and the output 21 of the recording clock. The operation of the phase meter is as follows. The inputs 18 and 19 of the formers 1 and 2 receive periodic signals, the phase difference between which is to be measured. The input shapers 1 and 2 at their outputs form pulsed consistency, the moments of occurrence of short I1 shulls. Which: correspond, for example, to the moments of positive transitions of input signals through the zero line. From the outputs of the formers 1 and 2, the pulse sequences are fed to the inputs of the time trigger 3, the output of which produces positive r 5 1-angle pulses, the duration of which is equal to the time shift between the signals fed to the input 18 relative to the signals fed to the input 19. and 2 signals are also fed to the inputs of the formers 11 and 12 of the reset and write blocking signals. From the output of the generator 6 to the inputs of synchronous counters 4 and 5, the drivers 11 and 12, 13 and 16 receives the signal frequency. The frequency of the clock generator is chosen so that in one period of the input signals, the phase difference between which / y is measured, fits 360 N periods of the clock frequency signal (frequency of filling), where n is an integer determining the resolution of the phase meter. Synchronous counters 4 and 5 continuously count P1ushulsov, arriving 1sh-1X from the generator's 6 waveform. At the moments of arrival at the input of generator 11 (12) from the output of generator 1 (2) of a short pulse, corresponding to the moment of transition input: south signal through the zero line, at the output of the forcing device 11 (12), a pulse of the duration of one clock frequency period is formed, which causes a reset of the system account | The chuck 4 (S), in order to prevent the loss of an iformat over the time duration of the reset reset pulse, is performed with a forced record of the unit. Thus, each of the counters continuously from the previous reset to the next, that is, from the previous one.

From the signal input at the fore / gate input. 1 (2) through the zero line to the subsequent ixi, recalculates the filling pulses coming from the output of the clock generator of the clock.

A strong start arrives at input 17 and enters transformers 13 and 16. On arrival through the trigger signal channel to inputs of drivers 13 and 16 during the first negative half-wave, generator 6 at the output of driver 13 forms a cft 1 short pulse arriving at the input of blocks 14 and 15, with the occurrence of which the information from counters 4 and 5 is copied into these blocks. If the trigger signal coincides in time with the moment the counters 4 or 5 are reset, the rewriting of information from counters 4 and 5 into blocks 14 and 15 is delayed. before the end of the process reset but. The delay is made by the driver 13 circuit when the pulses come from B; 1 inputs of the drivers 11 or 12. The memory blocks are connected to the output / w of difference difference unit 8, where the value recorded in block 14 is subtracted from the value recorded in block 15 That is, the value of fj - f is calculated, where f, U f 2 are the daily values of: the phases of the signals at inputs 18 and 19, respectively.

In this case, if, f, then the time trigger 3 is in the unit state to the value of the difference f. - f Q calculated by block 8 is transmitted through adder 9 to outputs 20 without change. If -P - f2. Flip-flop 3 is in the zero state, and 360 appears on the outputs of block 1O, and in the adder 9 the operation

360 - - fi).

which corresponds to the modulus of the value of the phase difference (4, -, p2,).

The obtained value of the phase difference appears on viy. 2.0.

Thus, this device makes it possible to measure the phase difference of two signals over a time that is significantly less than the duration of the iorode 3 and equal to the duration of one period of the filling signal, as well as to improve the measurement accuracy.

Claims (2)

1. A.V.S.N. 363933, M.kl.OO R 25/04, 05.20.71. 2. Auth. St. Ho 256862, Cl. & 01H25 / 00, 08/05/68.