SU514291A1

SU514291A1 - Extremely bit-binary extraction device

Info

Publication number: SU514291A1
Application number: SU1981565A
Authority: SU
Inventors: Сергей Андреевич Соколов; Виктор Викторович Крючков; Нот Филиппович Тафипольский
Original assignee: Предприятие П/Я Г-4097
Priority date: 1973-12-27
Filing date: 1973-12-27
Publication date: 1976-05-15

Description

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Известно устройство дл сравнени нескольких двоичлых чисел и выделени экстремального из них путем последовательного .поразр дного анализа, содержащее т/г-входовых элементов «ИЛИ, «/п-разр дные регистры дл хранени и сравни;вани чисел.A device is known for comparing several binary numbers and extracting the extremal of them by sequential bit analysis, containing t / r input elements "OR," / n-bit registers for storing and comparing;

В известном устройстве отсутствуют общие дл всех регистров выходы, с которых могут быть считаны коды экстремального числа и номера регИ|Стра, содержащего это число; кроме того, устройство характеризуетс лебольщим быстродействием.In the known device, there are no exits common to all registers from which codes of an extremal number and regIn | Stra numbers containing this number can be read; In addition, the device has a fast response rate.

Целью изобретени вл етс расщиреиие класса решаемых задач и повышение быстродействи . В предложенном устройстве это достигаетс тем, что оно содержит по т трехвходовых элементов «И и одному т-,входовому элементу «ИЛИ на каждое из двоичных чисел , лричем пр мые .выходы регистров поразр дно соединены с входами п-входовых элементов «ИЛИ, «HBepcHbie выходы каждого регистра соединены с первым входом соответствующих элементов «И, второй и третий входы которых .поразр дно соединены с ши-нами управл ющих сигналов и с выходами пвходовых элементов «ИЛИ соответственно, ВЫХОДЫ которых подключены ,к соответствующему выходу устройства, а выходы элементов «И каждого регистра соединены со входамиThe aim of the invention is to expand the class of tasks and improve speed. In the proposed device, this is achieved by the fact that it contains on t three-input elements "AND and one t-, the input element" OR to each of the binary numbers, the direct direct output of the registers is bit-wise connected to the inputs of the n-input elements "OR," The HBepcHbie outputs of each register are connected to the first input of the corresponding And elements, the second and third inputs of which are randomly connected to the control signal busses and to the outputs of the OR input elements, whose OUTPUTs are connected, to the corresponding output of the device, and the outputs of the elements “AND of each register are connected to the inputs

/й-входовых элементов «ИЛИ, выходы которых .подключены к соответствующему выходу устройства./ d-input elements "OR whose outputs. are connected to the corresponding output of the device.

Сущность изобретени заключаетс в том, что в случае неравенства исследуемых чисел в каком-либо разр де при поступлении соответствующего управл ющего сигнала на выходах схем «И этого разр да чисел, у которых в нем имеетс «О, по вл етс «1, котора The essence of the invention is that in the case of inequality of the investigated numbers in any category, upon receipt of the appropriate control signal at the outputs of the circuits "And this bit of numbers, which in it has" O, appears "1, which

через /и-входовые схемы «ИЛИ устанавливает в состо ние «О регистры этих чисел, исключа эти числа из дальнейшего пораз|р дного анализа. Вследствие этого по окончании поразр дного анализа на выходах «нвходовыхthrough the / and input circuits "OR sets to the state" About the registers of these numbers, excluding these numbers from further sequential analysis. As a result, at the end of the routine analysis at the outputs of the “input

схем «ИЛИ получаетс пр мой код максимального числа, а на выходах ш-входовых схем «ИЛИ - инверсный позиционный код номеров регистров, в которых записано это число.“OR” schemes get the direct code of the maximum number, and the outputs of the w-input schemes “OR” are the inverse position code of the numbers of registers in which this number is written.

На чертеже показана блок-схема предложенного устройства.The drawing shows a block diagram of the proposed device.

Оно содержит т (статических) регистров 1, в которые занисаны пр мые т-разр дные коды (дл случа выделени максимальногоIt contains t (static) registers 1, in which direct t-bit codes are assigned (for the case of the selection of the maximum

числа) сравниваемых двоичных чиселnumbers) compared binary numbers

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Claims

n-l "2 The first bit of these numbers is the highest. Writing codes of numbers into registers can be done by any known method. Each register has 3 and 3 “2 input circuits. Their outputs are connected to the t-: input circuit“ OR 3, the output of which is connected to the input of the installation in “About the same register. The direct outputs of all registers bitwise are connected to the inputs of П-1INPUT schemes “OR 4”, the outputs of which are also bitwise connected to the first inputs of the “AND

2. The second input of each element “AND 2 is connected to the inverse output of the corresponding register bit, and the third is connected to one of the buses i, Bx.i,“ Input 2, ... ”Input. In the absence of control signals on the buses "Bx.i," Bx.z ... "Bin.t, and consequently, on one of the inputs of the circuits" And 2, there is a voltage level corresponding to the logical "O. Therefore, at the outputs of the circuits "AND 2 and" OR 3 there is also an "O. In case of successive appearance on tires “Bx.i,“ Bx.z, ... “The input of control signals, the voltage level of which corresponds to the logical“ 1, occurs, starting from the highest order, a sequential bitwise analysis of the numbers under study. In case of inequality of numbers in the analyzed bits, i.e., if in this category all registers contain both “O and” 1, the setting is made to “About those registers that have this category registered as“ O. Let the values of the most significant bits of all numbers be equal to "O. In this case, at the output of the circuit “OR 4 high-order bits, and respectively, at one of the inputs of the circuits“ I 2, there is “O. When a control signal appears on the bus "Bx.i" at the outputs of the circuits "AND 2 and" OR 3, it remains "O and the state of the device does not change. In case the values of the most significant bits of all numbers are equal to "1, the state of the device when the control signal on the bus Bx.i does not change either, since the input of the circuits" And 2 connected to the inverse outputs of the higher bits Dov registers present "O. If there is a disconnect in the high order, then when a control signal arrives at the bus “Bx.i”, there occurs a match “1 at the inputs of the circuits” And 2 connected to the inverse outputs of those registers that have the “O” Therefore, at the outputs of these circuits “AND 2” and at the output of the corresponding circuits “OR 3” appears “1, and the registers for which“ O ”is written in the preceding bit are set to the“ O ”state (switching of the register triggers occurs when their installation voltage output corresponding to a logical "1). Then, as the control signals appear on the “Bx.z,“ Bx.z ... ”Tire buses, the analysis of all other bits is performed using the above algorithm. As a result, only those registers in which the number having the largest value is written are not set in "O", and the code of this number appears at the outputs of the "OR 4" circuits. At the outputs of the circuits "OR 3, referring to these registers, there will be" O, and at the outputs of the circuits "OR 3, referring to the other registers," 1. Thus, from the outputs of the “OR 4” circuits the direct value of the maximum number code can be read, and from the outputs of the “OR 3” circuits - the inverse value of the positional code of the numbers of registers in which this number is written. If it is required to select the minimum number from the studied numbers, then the information recording inputs in the registers switch the bus containing the inversions of the direct codes of the investigated numbers tliuzPt. Apparatus of the Invention A device for allocating an extreme of nm bit binary numbers, containing mn-input elements "OR", non-volatile registers, characterized in that, in order to expand the class of tasks and increase the speed of a device, it contains and one / p-input element "OR on each of binary numbers, with the direct outputs of the registers are bitwise connected to the inputs of the p-input elements" OR, the inverse outputs of each register are connected to the first input of the corresponding elements “And, the second and third inputs of which are serially connected to control signal buses and to the outputs of the input elements OR, respectively, the outputs of which are connected to the corresponding output of the device, and the outputs of the elements AND of each register are connected to the inputs of input inputs OR whose outputs are connected to the corresponding output of the device.

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