SU513516A1 - Phasing device - Google Patents

Description

Frequency 7 is connected to one of the inputs of the regenerating node 12, to the second input of which is connected the input of an arsenic node 1 to the input bus 13 of unregenerated information. To the second input of node 2, the reference bus is often connected to r 14, and the outputs of frequency divider 7 and regeneration node 12 are connected to the output buses 15 and 16 of the receive clock frequency and to the non-generated Iformatshg, respectively.

The device works as follows.

Unregenerated information from the communication channel is fed to the input bus 13. If the information is changed, frequency divider 7 through the elements OR 6 and AND 5 generates a signal, the reception clock frequency, which is fed to the output bus 15. If the information send the zero turns into a unit or vice versa, differentiating node 1 forms its front, and At the output of the Noise Protection Node 2, a single pulse is released, which, depending on the phase of the signal on bus 15, shifts the receive clock frequency to the lagging side (excluding one reference frequency pulse) or to the direction of caution. (by adding one pulse to the reference frequency).

In the mode ... the lag of information packages from the reception clock frequency should be delayed clock (frequency except for one pulse at the input: frequency divider 7.

For this, the pulse from node 2 through element I. 9 and inverters 8 and 4 prohibits the passage of the next l pulse of the reference frequency coming from the input bus 1 of the reference frequency 14. Delay knot 11 ensures simultaneous arrival of these signals on the element And 5. So at the input of frequency divider 7 one is excluded: a counting pulse, which delays the signal on bus 15 by one period of the reference frequency.

In order to advance the impulse information of the receive clock frequency is AND 9, which, through the delay node 1O and the element OR 6, provides a single pulse to the frequency divider 7

four

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| add-on, resulting in a clock frequency shifted sideways ahead. The 1O delay node ensures that the signals at the input element are synchronized.,

The regenerative node 12 transmits the regenerated information to the output bus 16, there are no crushing on the front in the colorant, there it is phased with the clock frequency of the reception. It works on the strobe

frequency divider 7, corresponding to the middle of the receive clock frequency. Thus, information pulses are delayed in the phasing device by a half-cycle clock frequency. For delay

The receive clock frequency is used at the same time as its inverse. Correction i of the phasing device occurs at the moment of reception of the fronts of information packages, therefore the polarity of the signal is as follows;

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Claims (1)

 Invention Formula A phasing device containing a differential node, the output of which is connected to the input of the anti-interference node, as well as a frequency divider, the output of which is connected to the regeneration node, connected 1 to the input of the differentiating node, that, in order to improve the accuracy of the settings, it additionally 35 | elements And, inverters, nodes zadbr: zhki and element OR, with the output node-); la protection, from interference through the first element, the first inverter, the second element B, the element OR, the frequency divider to the second 40, the inverter is connected to the second input of the first AND element, and through the third element the first delay node is connected to. the second input of the OR element, with the output of the frequency divider connected to the second 45 | input of the third element, And, to the input of the node protection from interference is connected to the input of the second. delay node, the output of which is connected to the second input of the second element And. SO