SU506853A1 - Device for dividing an n-bit binary code into three - Google Patents

Description

Table

Note: code 00 in any pair of crp.iinijpoBaaiibi. to zero.

On the output buses, 5 bits of the remainder are connected to the carry outputs of logic unit 4. The result of the division is saved on the output buses of the quotient and the remainder as long as the number code is stored in the register of the dividend.

For simplicity, consider in more detail the principle of operation of the device for an eight-bit code (see Table 1).

Let, for example, it is necessary to divide the binary code of the number 211 by 3 with an accuracy of two bits after the decimal point. In tenth form:

211: 3 70-.

Divisible in binary code, divided into groups of two bits, starting with the lower bits, has the form (see Table 2):

table 2

d7

Have

Have

(Yu: 01

Cvmma

bits corresponds to a partial quotient equal to

For code 11, the highest pair of divisible cfrufe bits from table I find the value of the partial quotient 1000000.00. For code 01

pairs of partial quotients will be 101.01, and for code 11 of the lowest rfjufo pair, 1.00.

Partially summed partial quotients, we find the result of dividing the eight-bit binary code of a number into three, also presented in binary code:

1,000,000.00 01.01

1000101.01 and

1000101.01

1.00

1000110.01

Since the fractional part of a partial private part has weights in multiples of / 3, the rule of summation of binary numbers does not apply to them, however, it is valid for integer parts. Therefore, when summing pairs of parts of the fractional part, it is necessary to use the rule of summation and formation of transfers (see Table 3).

Claims (1)

01 10 j 10 00 00 01 - in the taolice, there are cases when the transfer to the low-order bit of the sum of the integer parts of the numbers takes place in the pairwise summation of the fractional parts of partial quotients. Based on the data table. 1 and the above example, we can write the logical functions to find the values of the two particular bits as follows: 421-1 /2.--1+ P2i-2 (a; -f &;), (1) 72i-2 P21-2a (L (+ P2i (b; + c,) + +;, (2) and the logical functions by which the values of the transfers P are found, in the form: P2, - IC, .6, + Prt P-11- ; 1 + + P 2 / - vC;, P2i-4, P-2i-Pzi-2Ci + + Pzi-ibf. At the same time, to synthesize a logic unit, it is enough to use expressions (1) - (4). and no restrictions are imposed on the register. Thus, a device for dividing an n-type code into three consists of schemes of each of which comprises: 1) of the two-dividend register projectile loader; 2) into two binary decoder input and three outputs; 3) logical block operating in accordance with expressions (1) - (4). The proposed device, in contrast to the known one, contains a smaller number of elements, since it does not have a private shift register, a synchronization scheme, a memory of samples, and a cycle counter, and also, instead of a shift register of a dividend, a simpler, static register of dividend is used. The duration of the division operation in the proposed device is determined only by the speed of the elements used in the device. Apparatus of the Invention A device for dividing an n-bit binary code into three, containing a register of a dividend, the bits of which are divided into groups of two bits in each group, decryptors and logical blocks of the same type, characterized in that, in order to simplify the device and increase it speed, the outputs of the bits of the g-th group of bits of the register of the dividend are connected to the inputs of the g-th decoder (where 1 t -), the outputs of which are connected to the inputs of the f-ro logic unit, the output outputs of the i-ro logic unit are connected to the inputs (t -1) logical block transfers outputs of the first logic block output lines are connected to discharge residue rows, outputs bits private logical blocks are connected to the output of the private buses. f A / f Jl / mt m