SU487418A1 - Multi-level storage element - Google Patents

Description

The present invention relates to the field of computing, in particular, to storage elements and can be used in digital differential analyzers (CDA), in a number of digital computer devices with a decimal number system, as well as in 8-bit direct binary code converters. 4-2-1 per ten level code.

There are known multilevel storage elements (MES) made on integral numerical rulers with two openings per discharge, the cross sections of which between the openings of each discharge are equal to each other and two times smaller than the cross sections of the jumpers between the openings of adjacent discharges.

However, these elements do not allow the 8-4-2-1 binary-decimal code to be converted into a ten-level code, which significantly reduces their functionality and application.

The purpose of the invention is to expand the scope of application of the known storage element.

The goal is achieved by the fact that the tire of the first discharge is stitched opposite through both holes of the first discharge, the spike of the second discharge is stitched through the second hole of the same name, the tires of the third and fourth bits are stitched according to the corresponding pair of holes of the same discharge, the output winding is stitched oncoming

through the second holes of all bits and through the first holes of the third and fourth bits, and through both holes of the fourth bit it is stitched twice, and the read winding is stitched sequentially through a series of first and a number of second holes of all bits in one direction through the holes of odd bits and in the opposite direction through the holes of even bits. FIG. 1 shows a multi-level storage element; in fig. 2 - magnetic states of its jumpers.

FIG. 1, the following are labeled 1: an integral number ferrite ruler with four pairs of holes 1; the first holes corresponding to the first, second, third and fourth ones will be 2-5; the second holes corresponding to the first, second, third and fourth bits 6-9; read winding 10; tires of the first, second, third and fourth bits 11-14; output winding 15; elementary jumpers P 1 -FZ.

Integral numerical ferrite line 1, containing the first 2-5 and second 6-9

holes, respectively, of the first, second,

third and fourth bit stitched

opposite the first holes 2-5 and

A series of second holes 6-9 reading winding 10. The tire of the first discharge 11 is stitched

opposite the first 2 and second 6 holes of the first bit, the second bit 12 bus is stitched through the second 7 holes of the second bit, and the third and fourth bits tire is stitched according to the same holes of the third, fourth and fourth bits . The output winding 15 is stitched in opposite through holes 6-9, 5 and 3, and through holes 5 and 9 twice.

In the proposed multilevel memory element, five of the six possible steady states of the elementary area of this element containing one pair of holes of any discharge are used.

FIG. 2 shows five steady states, denoted by the letters a, b, c, d, and /. The presence of a maximum flow through any elementary jumper is indicated by two arrows pointing in one direction, and a flow equal to zero - by arrows pointing in opposite directions. The "left to right" direction in FIG. 2, and for the negative - the opposite.

Input signals are designated: 5i - signal of the first bit; 2 - second bit signal; Зз - signal of the third bit; S is the fourth bit signal; Ss read signal.

For the above five stable conditions in accordance with FIG. 1 is given a table of Ni 1 transitions from one state to another under the influence of input signals Si-S- ,.

Tcifj: vva 1

input

 .4 j, G

c and g: - a L:

. H C d

When determining the bit weights, a bit table is given for the transition table (Table 2).

Through and 11) denotes the maximum initial magnetic flux through the rth elementary jumper; Fcc is the maximum final magnetic flux through the rth elementary jumper.

Taking into account the maximum magnetic flux irirashii in the t-th jumper FMF-FCHP to the maximum flow in the -th jumper receive a relative prirash, magnetic flux in the ;; jumper;

d ,, fk-f., „, fch

From table 1 and 2 taking into account the continuity of the magnetic flux

Efu-o

and the law of total current

L1L

2 .-.

U-1

make a table of outputs table. 3, in which DF1, AF2 and DFZ are relative 45 increments of fluxes in the first, second and third jumpers, respectively.

The MSE, based on the principle of summation of elementary increments of magnetic fluxes, operates in two cycles. The initial state of an MSE is taken as the set of states of four elementary areas established by the action of the read signal Ss. Then, the elementary sections of the first and third bits are set to state a, and the elementary parts of the second and fourth bits are set to state b.

In the first clock cycle, depending on the input information presented in the forward binary code 8-4-2-1, certain Si-S signals, which establish elementary segments in the state corresponding to Table 2. In the second cycle, a readout signal S is received, which remagnets the elementary sections of the MZE into the states defined by Table 3, as a result, an emf signal, proportional to the total increment of the fluxes, determining either or other value of ten level number.

t

Subject invention

A multilevel storage element made on an integral numerical ferrite ruler with two holes per discharge, the cross sections of which are between each hole of each discharge are equal to each other and two times smaller than the cross section of jumpers with holes of neighboring bits, which means y and with the fact that, in order to expand the field of application, the tire of the first discharge is stitched in opposite through both holes of the first discharge, the tire of the second discharge is stitched through the second hole of the same discharge, tires of the third and fourth discharge of You agree through the corresponding pair of holes of the same bits, the output winding is stitched counter through the second holes of all bits and through the first holes of the third and fourth bits, and through both holes of the fourth bit it is stitched twice, and the read windings of iroshita sequentially through the first and a series of second holes of all bits in one direction through the holes of odd bits and in the reverse direction through holes of even bits.

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