SU487390A1 - Firmware processor - Google Patents

Description

one

The invention relates to the field of computer technology and is intended for use in digital computers.

Firmware processors are known that contain a firmware control unit, an arithmetic unit, a register unit, a split-cycle random access memory, a data register, an erase signal decoder, a write and read micro ops, and an arithmetic unit and a block of registers and write and read micro op operations.

A disadvantage of the known processors is that the time interval between the beginning of the read micro-op and the start of the micro-op write must be slightly less than or equal to the read time — the time from the moment of issuing the read micro-op until the information appears at the RAM output.

The aim of the invention is to simplify the operation of the processor.

This goal is achieved by introducing a data register control signal generating unit, the input of which is connected to the output of the read micro-operation decoder, and the output to the third input of the data register.

Functional diagram of the processor shown in the drawing.

Firmware processor contains firmware 1; an arithmetic unit 2 connected to a block of registers 3; random access memory 4 connected to the output of the block of registers 3; data register 5, connected to the arithmetic unit 2 and the RAM 4; micro-optics start-up unit 6 and micro-opex start-up unit 7 connected to main memory 4. These units are controlled by decoders, the inputs of which are connected to device 1. The outputs of the micro-operations decoder of the arithmetic unit 8 are connected to the arithmetic unit 2, the outputs of the micro-operations decoder control unit of registers 9 - to the block of registers 3. The outputs of the decoder of microoperations of reading 10 are connected to the unit 7 and the unit of formation of the control signal of the data register 11, the output of which is connected to the register 5. The output of the decoder of the signal erase 12 is connected to block 7, and the output of the decoder of the micro-operations of recording 13 is connected to the input of block G.

During the processor operation, the RAM 4 is accessed. When reading the information, the decoder 10 outputs a read micro-operation, which is fed to the block 7 and to the input of the block I. By that time

when readout information is output from the memory 4, the output of block 11 is a signal allowing the information to be entered into data register 5. Thereafter, the read information can be transmitted to register block 3 or arithmetic unit 2 for processing.

At the moment of time determined by the operation algorithm, the decoder 13 issues a recording micro-operation, and the entry into block 6. This micro-operation allows to store 4 processed information into memory or restore the contents of the cell that was destroyed during the micro-operation of reading.

In the case when it is necessary to erase the information B of the RAM 4, the decoder 12 generates an erase signal, which enters only in block 7.

The read information is not accepted in the data register b and is therefore lost, since the contents of the selected cell are destroyed. The write operation allows writing a new (in particular, zero), prepared in advance in data register 5, information in place of the old one.

Subject invention

A firmware processor containing a firmware control unit, an arithmetic unit, a register unit, a random access memory, a data register, decoders

erase signal, write and read micro ops, and arithmetic unit and register registers microoperations, write and read micro optics start blocks, where the outputs of the microprogram control unit are connected to the inputs of the erase signal decoders, write and read microoperations, and microoperations of the arithmetic unit and block

registers, the outputs of which are connected respectively to the first input of the read micro-operation start block, with the input of the micro-write start block, with the second input of the read micro-start block, with

the first inputs of the arithmetic unit and the register unit, the second input of which is connected to the output of the arithmetic unit and the first input of the data register, the output of which is connected to the second input of the arithmetic unit, the third input of which is connected to the output of the register unit and the first input of the RAM, the second input which is connected to the output of the micro-optics startup block, the third one with the output of the micro-ops startup block, and the output to the second data register input, characterized in that, in order to simplify the process crap, it contains the data register control signal generation unit, the input

which is connected to the output of the read micro-operation decoder, and the output - to the third input of the data register.