SU477412A1 - Device for testing logical subunits - Google Patents

Description

(54) DEVICE FOR INSPECTION OF LOGICAL SUBLOCKS

one

The proposed device relates to the field of digital control equipment and can be used in the manufacture of digital equipment or in the maintenance of computing systems.

Devices for testing logical sub-blocks are known, comprising a counter, an action register, a valve block, an input register, a control unit, an analysis and display unit, and a control unit.

A disadvantage of the known devices is the need for a reference block, an unacceptably long test time, or the need to construct special test programs for each type of logical sub-blocks.

The proposed device is characterized in that it comprises a switch of steps, a switch of the outputs, the first of which is connected to the outputs of the input register, and a second input to the second output of the control unit, an output valve whose first input is connected to the output of the switch of the outputs. The second input is connected to the first output of the control unit, and the output is connected to the input of the control unit. The output of the block of interchangeable constants is connected to the input of the output register, with the switch of stages, the valve block and the output register being made of a number of sections, and each section of the valve block and the output register is made of two subsections. The outlets of the subsections of the valve block are connected to the corresponding inputs of the subsections of the output register, and the outlets of the sections of the valve block to the outlets of the corresponding sections of the switchboard stages. The third output of the control unit is connected to the input of the block of interchangeable constants, and to the nerve inputs of the switch of the stages, the second inputs of which are connected to the output of the counter and the input of the node

management

Another difference of the proposed device is that in it the control unit contains a mode switch and a terminator connected in series

cycle, output counter, output decoder, ethane counter, and stage number decoder.

This allows the use of a single algorithm when testing various logical subunits. For subunits with a large number of inputs, it is possible to carry out checks in a relatively short time without developing special test programs using expensive software and without using reference subblocks.

Pa figs. 1 shows a block diagram of the proposed device; in fig. 2 is a block diagram of the control unit of the proposed device.

A device for testing logical subunits contains an impact unit on a monitored object 1, a state fixing node of outputs 2 and a control unit 3. Object 1 includes a counter 4, a switch of steps 5, a valve block 6 and subsections 7 and 8 of the output register of the action device. The fixing unit of the state of the outputs of the object 2 contains an input register 9, an output switch 10, an output valve 11, a control unit 12 and an analysis and display unit 13. The control unit 3 for communication with other units contains input buses 14, output clock buses 15, output reference buses 16, output buses "Monitoring of outputs 17 and block 18 of interchangeable constants. The control unit 3 comprises a master oscillator 19, a clock counter 20, a decoder for clock 21, a work type switch 22, a loop end decoder 23, an output counter 24, a decoder for outputs 25, a step counter 26, and a decoder for the step number 27.

When checking the combinational subunits, which corresponds to one of the positions of the switch stages, the proposed device works as follows.

Under the action of signals arriving at the input of counter 4 from the clock bus 15, the state of its output signals varies from 0.0, ..., O to 1.1, ..., 1. The test set corresponding to an arbitrarily chosen working tact, enters through the executive elements of subsection 7 to the inputs of the object. During the work cycle, the signal from the output of the object selected by the switch 10 is fed through the open valve of the output 11 to the control unit 12 (for example, it is summed up on the counter). After repeating this process 2 times, which corresponds to the enumeration of all test sets from 0.0, ..., O to 1.1, ..., 1, the process with the help of the control unit is stopped, and on the display and analysis block 13 it is highlighted and analyzed to determine the health and diagnosis of the cause of the failure of the test object, the sum of the units accumulated in the control 12. The counter 4 may be less than the number of outputs of the monitored subblock. Signals from block 18 are supplied to the remaining inputs. Then the switch of outputs 10 switches the input of the control node to the next output of the test object, the outputs of counter 4 are fed to other inputs of the subblock. During the time of filling the counter 4, the control node 12 generates a checksum, for example, the sum of units, serving as a criterion for the health of the second output and so on, until all outputs of the monitored subblock are checked. When checking subunits with logical memory (the second position of the switch 22), the work takes place in two cycles: preparatory and working. Due to the operation of the valve block 6, at the preparatory cycle, only a part of the signals from the output of counter 4 is supplied to the output register, and accordingly

only part (subsection) 8 of the output register works, part (subsection) 7 of the register is reset. Valve II is closed, so the control unit does not accumulate information.

The inputs of the logical memory elements of the object are connected to subsection 8 of the output register. Thus, in the preparatory cycle, the logical memory of the object is set to one of the possible conditions corresponding to the test set received from counter 4.

In the next working cycle, the state of the counter 4 remains unchanged, but under the action of the valve block 6, the subsection 8 of the output register is zeroed out, and the test set from the counter 4 is fed to the subsections 7.

In the working cycle, the combination part of the object circuit is subjected to the joint action of external signals from the subsection 7

output register and internal feedback signals corresponding to the state of the logical memory specified in the preparatory cycle.

The state of the counter 4 in the test mode

objects with logical memory - must remain unchanged during the preparatory and working cycles; after the counter 4 is filled, the part of the object corresponding to the selected set of its inputs and output will be checked on a full enumeration of the input signals for each of the possible states of the logical memory of the object.

The necessary sequence of operation of the blocks of the circuit is provided by: the master oscillator 19 of the control device, whose frequency determines the duration of the working cycle of the device; a clock counter 20, a clock decoder 21, and a kind of work switch 22, due to which the device operates in the test mode of purely combinational circuits and logic memory circuits; end of the loop 23, counter of the outputs 24 and the counter of the outputs 25, due to which

switching to the new output of the object after the end of the cycle of the counter 4.

Since the cycle time for iterating over the values of counter 4 very much depends on the number of its bits n, to increase the number of executive circuits of the output register without significantly increasing the test time, a switch of steps 5, a counter of steps 26, a decryptor of step numbers 27 and a block 18 of interchangeable constants are provided. At the beginning of the test, under the action of the stage switch, the signals from counter 4 arrive only at the first section of the output register executive circuits. All other actuating registers of the register under the action of the control unit 3 are given signals corresponding to the constant number 1 stored in block 18 of interchangeable constants. These signals ensure the absence of signals from unchecked

this stage of the subunit parts. The constant signals provide the sensitivity of the paths from the tested input poles to the monitored output. After completion of the stage, which corresponds to the receipt of the checksum for the given output, using the switch of stages 5, the outputs of the counter 4 are switched to the second group of executive circuits of the output register and the constant number 2 from the block 18 of interchangeable constants is called. The check is completed after passing all the steps.

Subject invention

Claims (2)

1. A device for testing logical subunits, containing a counter, an output register, a valve block, an input register, a control unit, an analysis and display unit, the inputs of which are connected to the outputs of the control unit, and a control unit, the first output of which is connected to the counter input and The first input of the valve block, characterized in that, in order to reduce the testing time and to achieve a uniform testing algorithm for various logical subunits, it comprises a switch of steps, a switch of the outputs, the first inputs of which are connected to the outputs the input register, and the second input - with the second output of the control unit, the valve the output, the first input of which is connected to the output of the switch of the outputs, the second input is connected to the first output of the control unit, and the output is connected to the input of the control node, the block of interchangeable constants whose output is connected to the input of the output register, with the switch of stages, the valve block and the output register made of a number of sections, and each section of the valve block and the output register is made of two subsections, the outputs of the subsections of the valve block are connected to the corresponding inputs of the output register subsections, and the inputs of the sections of the valve block are connected to the outputs of the corresponding sections of the switch, the third output of the control unit is connected to the input of the block of replaceable constants and the first inputs of the switch of the steps connected to the output of the counter and the input of the control unit. 2. The device according to claim 1, characterized in that, in order to reduce the test time and achieve a uniform test algorithm for various logical subunits, the control node contains a mode switch and a series of end-of-cycle decoder, output counter, output decoder, stage counter and decoder in series. stage numbers. 477412