JPH06342041A - Circuit for facilitating test of logic circuit - Google Patents

Abstract

PURPOSE:To judge whether a single degenerate fault exists or not. CONSTITUTION:A plurality of circuits 12 for testing are cascadeconnected regarding a check input CHI and a check output CHO. When an H status is input from a monitoring input TD, every circuit 12 for testing outputs to the check output CHO a logic status which is different according to a logic status from the check output CHO. In addition, when an L status is input from the monitoring input TD, a prescribed logic status is output to the check output CHO according to a logic status from the monitoring input TD. Consequently, any one status change out of monitoring inputs TD1 to TDn can be judged by a signal CH(n+1) at a final stage, and a single degenerate fault can be judged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit test facilitation circuit used for testing a test target logic circuit incorporated in, for example, a semiconductor integrated circuit. A logic circuit that is realized by a gate logic circuit and can be incorporated into a test target logic circuit, for example, in a semiconductor integrated circuit, or a test pattern that is automatically input to a test target logic circuit. The present invention relates to a logic circuit test facilitation circuit in which the logic circuit having a relatively small number of logic gates can be realized and can be incorporated into a test target logic circuit, for example, in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Generally, a logic circuit can be divided into a storage element (or a storage circuit) such as a flip-flop and a combinational circuit using a NAND logic gate or a NOR logic gate. For example, the logic circuit shown in FIG. 11 is configured by a total of four storage elements including flip-flops 72 and combinational circuit units 66a and 66b.

The combinational circuit is such that the output is immediately determined when the input is determined. The output at this time is determined by the combination of the logic gates used, and can be expressed by a predetermined logical expression. Therefore, the combinational circuit can be tested relatively easily using its logic equation. On the other hand, in the sequential circuit, since the flip-flops are connected to each other or the flip-flop and the combination circuit are connected in a complicated manner, the output state cannot be expressed by a simple logical expression. Therefore, testing such a sequential circuit is very difficult.

A test method called a scan path method is often used in order to facilitate the testing of the sequential circuit composed of the memory element and the combinational circuit. This is to switch a flip-flop, which is a storage element portion in a sequential circuit, from a combinational circuit portion thereof to one long shift register when testing the logic circuit. According to the test method of the scan path method, for example, all the flip-flops of the logic circuit to be tested in the integrated circuit are made into one shift register, and while inputting a serial test pattern into the shift register, Even a logic circuit equipped with can be tested relatively easily and efficiently.

A test pattern used for testing a logic circuit such as the scan path test method is generated by detection by a functional test, for example. For example, a failure of a logic gate or a node inside a logic circuit to be tested (hereinafter simply referred to as a test target logic circuit) is
This is to manually create (observable) a test pattern that appears in the output of the output buffer of the test target logic circuit.

On the other hand, there is a method called an internal scan method as a method of generating a test pattern which is used in such a scan path type test method. This is a computer simulation,
The required test pattern is automatically or semi-automatically generated.

[0007]

However, in the above-described test method of the scan path system, it has been time-consuming to determine the presence or absence of a single stuck-at fault. For example, when n flip-flops in the logic circuit to be tested store the logic state used to determine the presence / absence of a single stuck-at fault, in the scan path method, n
In the read cycle of the cycle, the logical states of such n flip-flops must be read sequentially,
It is very time consuming. Further, the logic state of each flip-flop read in this way must be sequentially compared with each expected logic state, and such determination also takes time.

Further, with respect to the generation of the test pattern used in such a scan path method or the like, there is a problem in each of the generation method by the functional test and the internal scan method.

For example, in the test pattern generation method based on the above-mentioned functional test, it is necessary for a test pattern creator to be skilled in order to detect failures of all logic gates and internal nodes of the logic circuit to be tested. There's a problem. In addition, such test pattern creation takes a very long time.

On the other hand, the internal scan method described above also
Computer simulation and a lot of manual work are required, which is time consuming. In addition, the number of test patterns generated is generally large.
Therefore, in a test using a test pattern generated by such an internal scan method, many test patterns must be sequentially executed, which causes a problem that the test time becomes long.

The first invention of the present application has been made to solve the above-mentioned conventional problems, and the determination of the presence or absence of a single stuck-at fault is realized by a logic circuit having a relatively small number of logic gates, and a test target logic circuit At the same time, it is a first object to provide a logic circuit test facilitation circuit which can be incorporated in, for example, a semiconductor integrated circuit.

Further, the second invention of the present application realizes automatic generation of a test pattern to be input to a test target logic circuit by a logic circuit having a relatively small number of logic gates, and incorporates it into a semiconductor integrated circuit together with the test target logic circuit. It is a second object of the present invention to provide a logic circuit test facilitation circuit capable of performing the above.

[0013]

The first invention of the present application has a monitor input TD for inputting a logic state of a test monitor portion to be monitored in a test target logic circuit, a check input CHI, and a check output CHO. If the logic state input from the monitor input TD is the H state, each of the test circuits differs depending on the logic state input from the check input CHI. The logic state is output to the check output CHO, and when the logic state input from the monitor input TD is L state, the logic state input from the monitor input TD is H state. The correspondence between the check input CHI and the check output CHO is different, and differs depending on the logic state input from the check input CHI. The physical state a monitor logical operation circuit for outputting to the check output CHO, further, a plurality of the test circuits may be cascaded with respect to said checking output CHO and the check input CHI,
The check output CHO of the final stage of the cascade connection is provided corresponding to a predetermined logic state input to the check input CHI of the first stage of the cascade connection.
It is possible to determine whether or not the logic states input to the monitor inputs TD of the monitor logic operation circuits are all the same as the respective expected logic states by determining the logic state output from the The first
It has achieved its purpose.

A second invention of the present application is a test output TQ connected to a desired test setting portion for setting a logic state in a test target logic circuit, and a setting input CI.
And a set output CO, and a plurality of test setting circuits having an initial setting input CL and a clock input CK, and each of the test setting circuits outputs the held logic state, and its output Q is the test output. A flip-flop connected to TQ and having its logic state initialized according to the input of the initial setting input CL, the setting input CI and the output Q of the flip-flop are input, and these setting input CI and output are input. A half adder for outputting a result S of addition with Q to an input D of the flip-flop and outputting a carry C of the addition to the setting output CO, further comprising a plurality of the test settings. A circuit is cascade-connected with respect to the setting input CI and the setting output CO, and is connected to the setting input CI of the first stage in a cascade connection. A logic state corresponding to a carry in the carry C of the half adder is input, the initial setting inputs CL of the plurality of test setting circuits are connected in parallel with each other, and a plurality of the test setting circuits are provided. The second purpose is achieved by connecting the respective clock inputs CK in parallel with each other.

Further, in the logic circuit test facilitation circuit of the first invention, a test in which each of the test circuits is connected to a desired test setting portion for setting a logic state in a test target logic circuit. The output circuit Q has an output TQ, a setting input CI and a setting output CO, an initial setting input CL and a clock input CK, and each of the test circuits outputs the held logic state. A flip-flop connected to the test output TQ and having its logic state initialized according to the input of the initial setting input CL, the setting input CI and the output Q of the flip-flop are input, and these setting inputs CI are input. The addition result S of the output Q and the output Q is output to the input D of the flip-flop, and the carry C of the addition is output to the setting output CO. It is those having a half adder,
Further, a plurality of the test circuits are cascaded with respect to the setting input CI and the setting output CO, and
The setting input CI of the first stage of the cascade connection
Is input with a logic state corresponding to presence of a carry in the carry C of the half adder, the initial setting inputs CL of the plurality of test setting circuits are connected in parallel with each other, and a plurality of the plurality of the initial setting inputs CL are connected. By connecting the clock inputs CK of the test setting circuits in parallel with each other,
In addition to achieving the first object, the second object is also achieved.

[0016]

First, the operation of the first invention of the present application will be described.

The above-mentioned single stuck-at fault is one failure model of the logic circuit to be tested, which is incorporated in a semiconductor integrated circuit, for example. The single stuck-at fault is a fault model in which one point in the logic circuit to be tested is fixed to the H state or L state logic state. The first aspect of the present invention focuses on such a single stuck-at fault and enables it to be detected by a logic circuit using fewer logic gates.

FIG. 1 is a block diagram showing the gist of the first invention.

In FIG. 1, the logic circuit test facilitation circuit of the present invention comprises a plurality of test circuits 12. Each of the test circuits 12 has a monitor input TD for inputting a logic state of a test monitor portion to be monitored of a test target logic circuit and a check input CH.
I and a check output CHO.

Furthermore, a plurality of such test circuits 12 are provided.
Is the check input CHI as shown in FIG.
And the check output CHO are connected in cascade. For example, in FIG. 1, a total of n test circuits 12 are cascade-connected.

For example, in FIG. 1, a predetermined logical state is input from the outside to the check input CHI of the first stage which is cascade-connected as described above.
The check output CHO of the test circuit 12 of the first stage is connected to the check input CHI of the test circuit 12 of the second stage and is CH2. In this way, the subsequent connections are also cascaded. Further, with respect to the test circuit 12 of the final stage, that is, the nth stage, the check output CHO of the test circuit 12 of the (n-1) th stage is connected to the check input CHI, which is CHn. . Further, the check output CHO of the nth stage outputs CH (n + 1) as a logical state used for determining the presence or absence of a single stuck-at fault.

In this way, the monitor input TD of each of the test circuits 12 connected in cascade.
Are respectively connected to the test monitor locations to be monitored in the circuit under test. For example, in FIG. 1, the monitor inputs TD of the respective test circuits 12 are TD1, TD2 ... T in order from the first stage.
It is Dn.

FIG. 2 is a block diagram showing the configuration of the test circuit used in the first invention.

As shown in FIG. 2, the test circuit 12 shown in FIG. 1 includes a monitor logic operation circuit 14. When the logic state input from the monitor input TD is the H state, the monitor logic operation circuit 14 first outputs a different logic state to the check output CHO depending on the logic state input from the check input CHI. Is output.

That is, when the logic state input from the monitor input TD is the H state, the pattern A in FIG.
According to the logic state input from the check input CHI, the check output CH
The logic state corresponding to O is output. Alternatively, when the H state is input from the monitor input TD in this way,
As shown in the pattern B of FIG. 2, a predetermined logic state is output to the check output CHO in accordance with the logic state input from the check input CHI.

On the other hand, when the logic state input from the monitor input TD becomes the L state, the monitor input TD
When the logic state input from the check input CHI is the H state, the check input CHI and the check output CHO have different correspondences and different logic states depending on the logic state input from the check input CHI. Output to the check output CHO.

That is, when the logic state input from the monitor input TD is the H state, the check output CHO according to the check input CHI according to the pattern A.
Is output, the monitor input TD
When the logical state input from the check input is the L state, a predetermined logical state is output to the check output CHO according to the logical state input from the check input CHI corresponding to the pattern B. On the other hand, when the logic state input from the monitor input TD is the H state, the pattern B
When the logical state of the check output CHO corresponding to the check input CHI is to be output according to the above, when the logical state of the L state is input from the monitor input TD, according to the pattern A. , The logical state of the check output CHO corresponding to the check input CHI is output.

As described above, in the test circuit 12 used in the first invention, if the logic state input to the check input CHI changes like the pattern A or the pattern B, the check is always performed. Output CHO
The logic state output from will also change.

Further, when the logic state input from the monitor input TD changes, if the pattern A is used before the change, the pattern B is used after the change. Therefore, if the pattern B is used before the change, the pattern A is used after the change. Therefore, if the logic state input to the monitor input TD changes in this way, the logic state output from the check output CHO of the test circuit 12 also changes.

Therefore, according to the first aspect of the present invention, when the logic state of the check input CHI from the test circuit 12 in the preceding stage to be cascade-connected is changed or the test target input by the test circuit 12 is changed. When the logic state input from the monitor input TD from the logic circuit changes, the logic state output from the check output CHO always changes in any case. Therefore, by deciding the logical state output from the check output CHO at the final stage of the cascade connection, the monitor input TD input to all the test circuits 12 connected in the cascade is degenerate. It can be determined whether or not there is a failure. This means that if a predetermined logic state is input to the check input CHI of the first stage of the cascade connection, one logic state of any one of the monitor inputs TD of the cascade connection is inverted due to a failure. If so, the logic state output from the check output CHO at the final stage is different from the expected logic state.

FIG. 3 shows a specific example of the monitor logic operation circuit used in the first invention.

Monitor logic operation circuit 1 shown in FIG.
4a to 14f are the check input CHI and the monitor input T, as described with reference to FIG.
According to the logic state input from D, the check output CHO outputs a predetermined logic state. The monitor logic operation circuit 14a is an EOR (exclusive OR) logic gate. Also, the other monitor logic operation circuits 14b-1
4f is an input or output of the EOR logic gate which is an inverted input or an inverted output.

The operation of the second invention of the present application will be described below.

In setting the test pattern by the conventional scan path method, the test pattern is set while operating the plurality of flip-flops as shift registers. The second invention of the present application sets a test pattern by a method completely different from such a setting method.

That is, the second invention is that a plurality of flip-flops used for setting a test pattern are operated as binary counters when setting the test pattern.

This corresponds to the test pattern to be set by forming a binary counter at the time of setting the test pattern and sequentially incrementing the counter value (increasing the value by "1"). The logic state output from each flip-flop (which constitutes a binary counter) corresponding to the predetermined value is set to a desired setting location where the logic state in the test target logic circuit is set. Is output as.

FIG. 4 is a block diagram showing the gist of the second invention.

As shown in FIG. 4, the setting circuit test facilitating circuit of the second invention comprises a plurality of test setting circuits 4.
2 is provided. These test setting circuits 42 respectively
A test output TQ connected to a desired test setting location for setting the logic state in the test target logic circuit.
, Setting input CI and setting output CO, and initial setting input C
L and clock input CK.

Further, such a plurality of the test setting circuits 42 are cascade-connected with respect to the setting input CI and the setting output CO. Further, the setting input CI of the first-stage test setting circuit 42 which is cascade-connected in this way has a logic state corresponding to the carry of the addition of the half adder included in the test setting circuit 42. Is entered.

The initial setting inputs CL of the plurality of test setting circuits 42 are connected in parallel with each other. Further, the clock inputs CK of each of the plurality of test setting circuits 42 are also connected in parallel. Further, those connected in parallel to each other in this way become the whole initial setting input CL and the whole clock input CK, respectively.

FIG. 5 is a block diagram showing the configuration of the test setting circuit used in the logic circuit test facilitation circuit of the second invention.

As shown in FIG. 5, the test setting circuit 42 shown in FIG. 4 is mainly composed of a flip-flop 46 and a half adder 44.

The output Q of the flip-flop 46, which outputs the held logic state, is connected to the test output TQ. The logic state held by the flip-flop 46 is initialized according to the input of the initialization input CL. For example, the flip-flop 46
Such an initial setting input CL included in is, for example, a clear input or a preset input. The clear input is for clearing the logic state held in the flip-flop. The preset input is also for setting the logic state held in the flip-flop.

The half adder 44 receives the setting input CI and the output Q of the flip-flop 46.
Further, the half adder 44 outputs the addition result S of the setting input CI and the output Q to the input D of the flip-flop. Further, the half adder 44 outputs the carry C of the addition to the setting output CO.

In the logic circuit test facilitation circuit of the second invention as described above, the respective test setting circuits 42 are provided.
Included in the flip-flop 46 and the half adder 4
4 can be operated as a binary counter by connecting a plurality of the test setting circuits 42 in cascade as described above. A binary counter like this
The respective test setting circuits 42 are connected to the respective test setting circuits 42 by the respective initial setting inputs CL of the test setting circuits 42 connected to the entire initial setting inputs CL (also connected to the initial setting input CL of the flip-flop 46). It is possible to collectively set the retained logical states.

For example, when such an initial setting input CL is the above-mentioned clear input, the logical state corresponding to "0" is collectively set in all the flip-flops 46 by such an initial setting input CL. You can After this, each flip-flop 46 of the test setting circuit 42 connected to the entire clock input CK.
By sequentially inputting the clock pulse from the clock input CK of 1, the counter values stored in the plurality of flip-flops 46 that are cascade-connected and operate as a binary counter can be sequentially incremented. Thereby, the counter value corresponding to the test pattern to be set can be obtained.

Further, for example, the above-mentioned initial setting input C
Even when L is the preset input as described above, the counter value corresponding to the test pattern to be set can be obtained. That is, after such an initial setting input CL which is a preset input, the counter value of what is regarded as a binary counter is set to the maximum value (all bits are "1"), and then clock pulses are sequentially input from the clock input CK. , The counter value is sequentially incremented.

Therefore, in the present invention, as described above, after the counter value is initialized by the initial setting input CL (for example, the counter value is set to "0"), the necessary number of clock pulses is input to the clock. By inputting to CK, the counter value corresponding to the desired test pattern can be obtained. In addition, corresponding to such a counter value,
From the test outputs TQ1 to TQn shown in FIG. 4, it is possible to set the logic state of a desired test pattern to a desired test setting location in the logic circuit to be tested.
Therefore, according to the second aspect of the present invention, the automatic generation of the test pattern to be input to the test target logic circuit can be realized by the logic circuit using a relatively small number of logic gates.

Now, let us consider setting of test patterns at desired test setting locations in a total of four test target logic circuits. In the scan path method described above as the prior art, a total of four shift operations must be performed in order to set the value of the shift register by a total of four flip-flops provided corresponding to a total of four test setting locations. I have to. For example, in the case of inputting all possible test patterns corresponding to all possible combinations of logical states for a total of four test setting locations, 2 ⁴ = 16 times only, 4 times as described above. Must shift. In other words, by the time the test using all possible test patterns is completed, (4 x
2 ⁴ = 64) shift operations must be performed.

In comparison with this, when the second invention is applied, a total of four test patterns for a total of four desired test setting locations are performed for all possible combinations. It is only necessary to input a total of 16 clock pulses to the clock input CK of the test setting circuit 42. That is, the number of clock pulses of 1/4 of the scan path method described above may be used. This is a total of 4
This is because the total (2 ⁴ = 16) combinations of test patterns at each test setting location are sequentially set every time a clock pulse is input to the clock input CK.
That is, when one clock pulse is input with a certain counter value corresponding to a certain test pattern, the counter value corresponding to the next test pattern is obtained.

As described above, according to the second invention, as compared with the conventional scan path type test method described above,
It is also possible to obtain an effect that the test time by the generated test pattern can be shortened.

The first invention and the second invention are not limited to this, but it is also possible to apply the first invention and the second invention in combination. For example,
As with the test circuit 12a shown in FIG. 6, the monitor logic operation circuit 14 to which the first invention is applied, and the flip-flop 46 and the half adder 44 to which the second invention is applied are also provided. May be. In this way, when the first invention is applied and the second invention is also applied, the first object can be achieved, and
The second object can also be achieved. Further, when the first invention and the second invention are applied as described above, the test pattern can be efficiently set by the synergistic effect of improving the workability, and the single stuck-at fault as described above is effective. Therefore, it is possible to effectively test the test target logic circuit incorporated in the semiconductor integrated circuit, for example.

[0053]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 7 is a logic circuit diagram of a test circuit used in the first and second embodiments to which the first and second inventions are applied.

The test circuit shown in FIG. 7 is applied with the first invention and the second invention as in the case of FIG. Further, as shown in FIG. 7, the test setting circuit used in the first and second embodiments is mainly composed of EOR logic gates 14a and 44.
b, AND logic gate 44c, selector 62, D
Type flip-flop 46. In particular, the EOR logic gate 44b and the AND logic gate 44c form a half adder 44a.

First, the EOR logic gate 14a corresponds to the monitor logic operation circuit 14 shown in FIG. When the monitor input TD is in the H state, the EOR logic gate 14a outputs a predetermined logic state from the check output CHO according to the check input CHI as shown in the pattern B shown in FIG. On the other hand, the EOR logic gate 14a outputs a predetermined logic state to the check output CHO according to the check input CHI as shown in the pattern A of FIG. 2 when the monitor input TD is in the L state. .

Next, in the half adder 44a, the EOR logic gate 44b performs 1-bit binary addition of the setting input CI and the output Q of the D-type flip-flop 46, and the addition result. The S is output to the input 1 of the selector 62. In the half adder 44a,
The AND logic gate 44c calculates the carry C at the time of addition of the setting input CI and the output Q of the D-type flip-flop 46. The carry C is output to the test circuit of the next stage as the setting output CO of the test circuit.

The selector 62 has inputs 0 and 1
, Input X, and output U. The selector 62 is
According to the input X, either the input 0 or the input 1 is selected, and the logic state of the selected one is output to the output U. That is, when the H state (“1”) is input from the input X, the EO
It selects the output of the R logic gate 44b and outputs its logic state to the output U. On the other hand, when the input X is in the L state (“0”), the selector 62 selects the monitor input TD and outputs its logic state to the output U. A mode signal MD is input to the input X of the selector 62. Regarding the mode signal MD, the L state (“0”) is the normal mode, and the H state (“1”) is the test mode.

The flip-flop 46 has an input D,
It has a clear input CL and a clock input CK, and an output Q. When the clock input CK rises, the D-type flip-flop 46 holds the logic state input to the input D and outputs the held logic state to the output Q. Further, the D-type flip-flop 46 sets the held logical state to the L state (“0”) when the clear input CL is in the L state. Further, the output Q of the D-type flip-flop 46 is connected to the test output TQ of the test setting circuit and also connected to one input of each of the EOR logic gate 44b and the AND logic gate 44c. Has been done.

FIG. 8 is a logic circuit diagram of the first embodiment.

The logic circuit shown in FIG. 8 is divided into a storage element and a combination circuit. That is, the combination circuit is composed of combination circuit units 66a and 66b. On the other hand, the memory element portion has a total of six test circuits 12b. These test circuits 12b have been described above with reference to FIG. In particular, in the test circuit 12b, when the mode signal MD is in the L state,
The test circuit 12b is configured as a D flip-flop. That is, when the mode signal MD is in the L state, the D circuit included in each of the test circuits 12b is
The type flip-flop 46 has its input D and its output Q connected to the combinational circuit sections 66a and 66b. Therefore, when the mode signal MD is in the L state in this way,
The circuit shown in FIG. 8 as a whole performs the same operation as the circuit shown in FIG. 11 as a whole.

On the other hand, these six test circuits 12b in total are cascaded with respect to the check input CHI and the check output CHO, and
The setting input CI and the setting output CO are also connected in cascade.

Therefore, in the present embodiment, when the first invention is applied and a predetermined logic state is input to the check input CHI of the test circuit 12b of the first stage, that is, the signal CH1, the By monitoring the logic state output from the check output CHO of the test setting circuit at the final stage, that is, the logic state of the signal CH7, it is possible to diagnose a single stuck-at fault in the combinational circuit units 66a and 66b. . That is, if the logic state of the signal CH7 output corresponding to the logic state of the signal CH1 is the same as the expected logic state, there is no failure, and if it is different from the expected logic state. It is said that there is a single stuck-at fault.

Further, in this embodiment, it is possible to apply the second invention and easily set the test pattern in the combinational circuit section 42b or the like. This is first
By setting the clear input CL to the L state, the logical state held by all the D-type flip-flops 46 included in the six test circuits 12b is set to the L state. Then, after the clear input CL is brought to the H state again, clock pulses are sequentially input from the clock input CK, so that the D-type flip-flops 46 included in the six test circuits 12b in total have 6 digits. As a binary binary counter, the counter value is sequentially incremented. According to the counter value thus incremented, the corresponding logic state is output from the output Q of each of the test circuits 12b. Therefore, with such an output Q, it is possible to set the test pattern of the combinational circuit section 66b and the like.

FIG. 9 is a logic circuit diagram of the second embodiment.

Also in the second embodiment, the test circuit 12b shown in FIG. 7 to which the first invention and the second invention are applied is used. Particularly, in the second embodiment, a total of four test circuits 12b are used. The operation of the second embodiment is almost the same as the operation of the first embodiment, but the number of the test circuits 12b used is different.

FIG. 10 is a time chart showing the operation of the second embodiment.

As shown in this time chart, in the second embodiment, first, the mode signal MD is set to the H state and the signal C1 is also set to the H state. After this,
By setting the clear input signal CL to the L state for a predetermined time, all the outputs Q output from each of the four test circuits 12b become "0".

After this, the first clock input CK
The output Q0 becomes "1" and the other outputs Q1 to Q3 remain "0" at the rising edge of. After that, at the next rise of the clock input CK, the output Q0 becomes "0" again, the output Q1 becomes "1", and the other outputs Q2 and Q3 remain "0". Thus, every time the clock input CK rises, the output Q
The logical states according to the counter values output from 0 to Q3 are sequentially incremented from "0" to "15".

As described above, according to the first and second embodiments, by applying the first invention, the presence or absence of a single stuck-at fault can be determined by a logic circuit having a relatively small number of logic gates. It can be carried out. Also, applying the second invention,
It is possible to automatically generate a test pattern to be input to the logic circuit to be tested, that is, the combinational circuit section 66b or the like.

The first and second embodiments are as follows.
It can be easily applied to existing logic circuits such as the conventional logic circuit shown in FIG. That is, for example, the D-type flip-flop 7 shown in FIG.
2 is replaced by the test circuit 12b shown in FIG. 7 or the like, so that the first invention and the second invention can be easily performed.
The invention can be applied. That is, the first invention and the second invention can be easily implemented by using the test circuit 12b even for a conventional logic circuit which is not particularly considered for the determination of a single stuck-at fault or the setting of a test pattern. It is possible to apply.

[0072]

As described above, according to the first aspect of the invention, the presence or absence of a single stuck-at fault can be determined by a logic circuit having a relatively small number of logic gates. It is possible to obtain an excellent effect that a logic circuit test facilitation circuit that can be incorporated in a circuit can be provided. Further, according to the second aspect of the invention, it is possible to provide a logic circuit test facilitation circuit capable of realizing automatic generation of a test pattern to be input to the test target logic circuit with a logic circuit having a relatively small number of logic gates. It is also possible to obtain an excellent effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing the gist of a first invention of the present application.

FIG. 2 is a block diagram of a test circuit used in the first invention.

FIG. 3 is a logic circuit diagram showing a specific example of a monitor logic operation circuit in the test circuit of the first invention.

FIG. 4 is a block diagram showing the gist of a second invention of the present application.

FIG. 5 is a logic circuit diagram of a test setting circuit used in the second invention.

FIG. 6 is a circuit diagram of a test circuit in which the first invention and the second invention are implemented in combination.

FIG. 7 is a logic circuit diagram of a test circuit used in the first embodiment and the second embodiment to which the first invention and the second invention are applied.

FIG. 8 is a logic circuit diagram of the first embodiment.

FIG. 9 is a logic circuit diagram of the second embodiment.

FIG. 10 is a time chart showing the operation of the second embodiment.

FIG. 11 is a logic circuit diagram of an example of a conventional logic circuit including a sequential circuit and a combination circuit.

[Explanation of symbols]

 12, 12a, 12b ... Test circuit 14, 14a-14f ... Monitor logic operation circuit 42 ... Test setting circuit 44, 44a ... Half adder 46, 72 ... D-type flip-flop 62 ... Multiplexer 66a-66d ... Combination circuit section

Claims (3)

[Claims] 1. A monitor input TD for inputting a logic state of a test monitor portion to be monitored in a test target logic circuit.
A plurality of test circuits each having a check input CHI and a check output CHO, and each of the test circuits has the monitor input TD.
When the logic state input from the check input HI is the H state, a different logic state is output to the check output CHO according to the logic state input from the check input CHI and the logic input from the monitor input TD. When the state is the L state, the check input CHI is different from the check input CHI and the check output CHO when the logic state input from the monitor input TD is the H state, which is different from the above. A check logic operation circuit for outputting a different logic state to the check output CHO in accordance with a logic state input from the check input C;
HI and the check output CHO are cascade-connected, and corresponding to a predetermined logic state input to the check input CHI of the first stage of the cascade connection, the check of the last stage of the cascade connection is performed. Output CHO
It is possible to determine whether or not the logic states input to the monitor inputs TD of the monitor logic operation circuits are all the same as the respective expected logic states by determining the logic state output from the monitor logic operation circuit. A logic circuit test facilitating circuit. 2. A test output TQ, a setting input CI and a setting output CO, an initial setting input CL and a clock input, which are connected to a desired test setting portion for setting a logic state in a logic circuit to be tested. CK and a plurality of test setting circuits, and each of the test setting circuits outputs the held logic state whose output Q is connected to the test output TQ, and the input of the initial setting input CL. In accordance with the above, a flip-flop whose logical state to be held is initialized, the setting input CI and the output Q of the flip-flop are input, and the addition result S of the setting input CI and the output Q is input to the input D of the flip-flop. A half adder for outputting the carry C of the addition to the setting output CO, further comprising a plurality of the test settings. Road is, the setting input CI
And the setting output CO are cascade-connected,
A logic state corresponding to the presence of a carry in the carry C of the half adder is input to the setting input CI of the first stage of the cascade connection, and A logic circuit test facilitation circuit, wherein initial setting inputs CL are connected in parallel with each other, and the clock inputs CK of each of the plurality of test setting circuits are connected in parallel with each other. 3. The test output TQ connected to a desired test setting portion for setting a logic state in a test target logic circuit, a setting input CI, and a setting input CI according to claim 1. Setting output CO, initial setting input CL and clock input CK
And each of the test circuits outputs the held logic state, and its output Q is the test output TQ.
A flip-flop connected to the input terminal of the flip-flop, the logic state of which is held according to the input of the initial setting input CL is initialized, and the setting input CI and the output Q of the flip-flop are input, and the setting input CI and the output Q are input. And a half adder for outputting the addition result S to the input D of the flip-flop and the carry C of the addition to the setting output CO, further comprising a plurality of the test circuits. Are cascaded with respect to the setting input CI and the setting output CO, and
The setting input CI of the first stage of the cascade connection
Is input with a logic state corresponding to presence of a carry in the carry C of the half adder, the initial setting inputs CL of the plurality of test setting circuits are connected in parallel to each other, and A logic circuit test facilitating circuit, wherein the clock inputs CK of the respective test setting circuits are connected in parallel with each other.