SU474004A1 - Device for dividing binary numbers - Google Patents

Description

of the private switch trigger and with the inputs of the third OR circuit, whose output through the first delay element is connected to the inputs of the first OR circuit and the third control trigger, the output of the latter is connected via the second OR circuit to the input of the fifth valve. The inputs of the fourth and fifth valves are connected via a second delay element with the output of the comparison circuit. The output of the fifth valve is connected to the input of the fourth control trigger, the output of which is connected to the output valves of the binary-decimal counter.

Diagram of the device shown in the drawing.

The device contains a generator of 1 constant frequency pulses / o, a divider code to frequency converter 2 (performed using a counter, a register and a comparison circuit), an r-tetradic binary-decimal counter 3 (taken to be three), a divisor register 4, binary counter 5, comparison circuit 6, frequency dividers 7 by ten, switch 8 (containing triggers 9, ventli 10 and OR 11), analysis circuit 12 (containing inverters 13 and And 14 circuits), additional P1LI circuits 15, combining outputs of a binary-decimal counter for tetrads, controlling e triggers 16, 17, 18 and 19, output valves 20, valves 21, 22, 23, 24 and 25, OR 26, 27 and 28 schemes, delay elements 29 and 30, and indicators 31, 32 and 33 .

The operation of the device is carried out in one or two cycles, depending on the order of the obtained quotient.

Initially, divider codes Aj and divisible N are entered into the device over buses 34 and 35. In this case, the divider code is converted in converter 2 to the frequency of pulses.

In the initial state, the control triggers 16 and 17 are in the state "O. The start-up command via bus 36 controls triggers 16 and 17 to state 1, and triggers 9, 18, and 19, and counters 3 and 5 to state O. In doing so, the valves 21, 22 and 23 are opened, and the valves 10 and 20 are closed. The input of the binary-decimal counter 3 receives impulses of frequency fi, and the input of binary counter 5 receives frequency impulses / o through gate 21, the OR 11 n gate 23. When the counter 5 reaches the code equal to the divisible code, the output of the circuit By comparison, a pulse is generated which transfers the control triggers 16 and 17 to the state "O." At the same time, the valves 21, 22 and 23 are closed, and the flow of pulses to the counters 3 and 5 is stopped. In binary-decimal counter 3, a private code is generated.

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The pulse from the output of the comparison circuit 6 also flows through the delay element 30 to the gates 23 and 24.

Further, the device is controlled depending on the degree of filling of the tetrads of the binary-decimal counter 3, i.e., in the order of part. In this case, for the case of a three-tethered binary-decimal counter 3, four situations are possible

quotient (see the table, where A, B, and C are the decimal digits of the quotient, and A 7 0). In the case of (situation a), when the quotient in the binary-ten counter 3 is three-digit (ABC), i.e. all the tetrads

the counter 3 is filled, at the output of the additional circuit OR 15 of the leading tetrad of the binary-decimal counter 3 a single potential is formed, which through the circuit OR 27 opens the vent 25. Then the pulse from the output of the delay element 30 goes through the gate 25 to the control trigger 19 and puts it in the state "1, while the output valves 20 are opened, the code of the private jV. enters the output device.

Thus, the operation of the device is completed in one cycle.

If the quotient formed has the number of significant digits less than three, i.e., the older tetrad of the binary-decimal counter 3 is not filled (situations b, in or in table 1), then the output of the additional scheme OR 15 of the older tetrad has zero potential , at the same time at the output of the inverter 13 of the analysis circuit 12 corresponding to

the highest tetrade of the binary-decimal counter 3, a single potential is formed, which opens the gate 24. In this case, the pulse from the output of the delay element 30 flows through the gate 24 to the control

input circuit 12 analysis. The analysis circuit 12 is constructed so that the pulse appears at one of its outputs 37, 38 or 39, depending on the order of the quotient.

Since the senior tetrad is not filled

the binary-decimal counter 3, in the case (situation b), when the quotient formed in the binary-decimal counter 3 is two-digit ("AB"), a pulse is formed at the output 39 of the analysis circuit 12 and is fed to the indicator 33 This switch also switches the corresponding trigger 9 of switch 8 to the state “b. This opens the corresponding valve 10 of the switch 8. This same pulse through the scheme "OR

28 and the delay element 29 transfers the control triggers 16, 18 to the state “B” and the counters 3 and 5 to the state O. The valves 22, 23 and 25 open. The second cycle of the device operation is performed. The binary-decimal counter 3 receives the frequency pulses / j, and

to binary counter 5 - frequency pulses / about 10 from the output 40 of the frequency divider 7 through the open valve 10 and the circuit “OR AND switch 8 and valve 23. At the output of the circuit 6

the comparison, an impulse is formed which transfers the control trigger 16 to the state "O. At the same time, the lines 22 and 23 are closed. The impulse from the output of the comparison circuit 6 also flows through the delay element 30 and the valve 25 to the control trigger 19 and transfers it to the state "1. At the same time, weekends of 20 are open, and private

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from binary-decimal counter 3 is fed to the output device.

In the case of (situation C), when the quotient formed in binary-decimal counter 3 is unambiguous ("O" OA), since two old tetrads of binary-decimal counter 3 are not filled, the pulse is formed at the output 38 of circuit 12 analysis, arrives at the comma-private quantizer 32, and switches the corresponding trigger 9 of the switch 8 to the state "1. Further, the device works in the same way as in the case of situation b, but the binary counter 5 receives pulses of the frequency fo / 100 from the output 41 of the frequency divider 7, and the output of the device receives the quotient.

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in the case (situation d), when none of the tetrads of the binary-decimal counter 3 is filled, a pulse is formed at the output 37 of the analysis circuit 12, is sent to the indicator 31 of the position of the second partial, etc., the correspondingly considered situation but at the input of binary counter 5, frequency pulses / 0/1000 are output from the output 42 of the frequency divider 7, and a quotient is formed

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which, regardless of its order, goes to the output of the device.

The delay elements 29 and 30 ensure the sequential operation of individual components of the device, eliminating false alarms.

Situations of private

Subject of the Invention A device for dividing binary numbers, comprising a pulse generator, the output of which is connected to the inputs of a divider-to-frequency code converter, a first Veptpl and a chain of serially connected frequency dividers, a binary-decimal counter,

the input of which through the second valve is connected to the output of the divider-to-frequency converter, the switchboard triggered by the switches and the OR circuit, whose input is connected to the output of the first valve, and the outputs of the frequency dividers are connected to the corresponding information inputs of the switchboard, the output of which is through the third the gate is connected to the input of a binary counter, a comparison circuit whose inputs are connected to

the outputs of the register of the divisible and binary counter, the first crank trigger, the output of which is connected to the inputs of the second and third valves, the second control trigger, the output of which is connected to the input of the first valve, the Start tab, connected to the installation inputs of the second, third and fourth control triggers, triggers of the switch and through the first circuit. P1LI - with the installation inputs of the second control trigger, binary and binary-decimal counters, the output of the comparison circuit is connected to the inputs of the first and second controls l constituent triggers analysis circuit configured to inverters and circuits "And circuit" OR

gates, delay elements and indicators of the position of a comma-private quotient, characterized in that, in order to increase the accuracy of dividing, the outputs of a tetrad. binary-decimal counter are connected to the inputs of the corresponding

additional circuits “OR, the output of the additional circuit“ OR the i-th tetrad is connected through the corresponding inverter of the analysis circuit with the input of the circuit “AND the 1st tetrad and the inputs of the circuits“ AND all previous junior

the tetrads and the mediocre are connected to the input of the schema “We” and the subsequent elder tetrade, the output of the additional circuit “OR the older tetrad” is directly connected to the input of the second circuit “RSHI and through the corresponding inverter of the analysis circuit - to the input of the fourth valve, the output of which And, the latter are connected to the inputs of the corresponding indicators of the position of the comma of the private quotient, the switch triggers and to the inputs of the third OR circuit, the output of which through the first delay element is connected to the inputs of the first OR circuit the third control trigger, the output of the latter is connected via the second circuit

"OR with the input of the fifth valve, the inputs of the fourth and fifth valves are connected via a second delay element to the output of the comparison circuit. The output and that valve are connected to the input of the fourth control trigger,

the output of which is connected to the output valves.

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