SU455501A1 - Interference-Coding Device - Google Patents

Description

one

This invention relates to telegraph communication.

A device for error-correcting coding is known, which uses multi-position coding of binary information, containing a source code register and elementary parcel generators.

The purpose of the invention is to increase the reliability of transmission.

This is achieved by the fact that in the proposed device each pair of neighboring triggers of the source code register is connected to the input of the decoder, and the outputs of all the decoders are connected to the switching nodes through the "And" controlled by the distributor circuits, and the combined generators are connected to the second inputs. the outputs of the switching nodes are the output of the device.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2-time diagram of his work.

Register 1 of the source code consists of static triggers 2i, 22, ..., 2 „. The number of triggers n depends on the length of the binary code. The load of the flip-flops 2i, 22, ..., 2 "are decoders 3 (32, ..., 3"). The number of decoders is equal to the number of register triggers 1. Each decoder 3 |, Over, ..., 3 „has four outputs d, d, d, and d.

The outputs of the decoders are connected to the logic circuits "AND 4. To the second inputs of these circuits" And the distributor cells 5 are connected. The distributor 5 has an input b for clock pulses and contains 5, 52, - .., 5, cells; . Each cell 5, the distributor is connected immediately to the four logic circuits "And i-ro decoder 3, (where 1 i p).

The outputs of all decoders through the logic circuit "And are combined and connected to the switching nodes 6. The pulses of the transformed code are formed using the generators 7 elementary parcels. Four oscillators are used for this, which have voltage And /, U, and U.

These voltages are through switching

nodes 6 are supplied in line 8. The code combination is constructed as follows: units can take positive values of the voltages f / i and U, and. The zeros take on negative stresses / 3 and U (where / 4 | j C / s |). In absolute value | t / i | | (7z | and 1C / 2 | and.

The value Ui is assigned to a unit when it is followed again by a unit. The last unit, the next one in the code combination, i.e., the unit for which

the null parcel follows, assigns the value of Uz. Similarly, the values of the voltages and the null parcels are assigned. In a code combination, a zero parcel is assigned a value of U in the case when it is followed again by a null, and a null parcel, followed by a one, is assigned a value of voltages t / 4 (fit. 2, a and b).

The device works as follows.

The source code is written to register 1. The code pulses are memorized by flip-flops 22, ..., 2. The decoder 3i is connected to the outputs of the flip-flops 2i and 22, the decoder is connected to the flip-flops 22 and 2z, etc. The last decoder is 2 "connected to the flip-flops 2" and 2i.

A voltage is set at one of the four outputs d, d, rfa, or d of each decoder. On which of these four outputs there will be a voltage, depends on the state of the triggers to which this decoder is connected. After writing the code, register 1 is applied to register 1 and pulses to the input b of the distributor 5. After the first pulse from cell 5i, distribute .. 5 the voltage is applied to four PI circuits to which the outputs of the first decoder 3 are connected.

At the output of one circuit .P1, a voltage appears that controls one of the four switches, their nodes 6. The latter outputs voltage 8 from the corresponding generator 7 to the line 8. After the second clock pulse at the input b of the distributor 5, the voltage from the output cell 5 removed

the output of cell 52 appears. This voltage is applied to the four AND circuits to which the outputs of the second decoder 32 are connected.

At the output of one of these four circuits, the voltage appears. It is also applied to one of the four switching nodes 6. With this node, the voltage from the corresponding

generator 7, etc., until all code has been transmitted to the line. FIG. 2, and a conventional binary code is shown, which is written to register 1, and FIG. 2, b-binary code with four levels, which is obtained in line 8.

Subject invention

An error-correcting coding device using multi-position coding of binary information, containing a source code register and elementary parcel generators, characterized in that

In order to increase the reliability of the transmission, each pair of neighboring triggers of the source code register is connected to the decoder input, and the outputs of all decoders are controlled by the distributor, connected to the switching nodes, the second inputs of which are connected to the corresponding headers parcels, and the combined outputs of the switching nodes are the output of the device.

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