SU448605A1 - Output stage - Google Patents

Description

one

The invention relates to a pulse technique and can be used as a generator of powerful binary signals.

The output stage is known, which contains a control and output transistor switches connected according to a common emitter circuit, and an emitter follower, the output of which is connected to the collector of the output switch transistor and the input to the output of the control key.

This cascade does not exclude through current.

The purpose of the invention is to eliminate through current.

To do this, the cascade includes the AND and OR circuits and a delay element whose output is connected to the inputs of the AND and OR circuits. The second inputs of the AND and OR circuit are combined with the inputs of the delay element, and the outputs are connected to the inputs of the control and output keys, respectively.

FIG. 1 shows a block diagram of the proposed output stage.

The output stage contains control and output transistor switches made on transistors 1 and 2, respectively, connected according to the circuit with a common emitter. The emitter follower output of transistor 3 is connected to the collector of transistor 2, and the input is connected to the output of the control key

transistor 1. The output of the delay element 4 is connected to the inputs of the circuits “AND 5 and“ OR 6, the second inputs of which are combined with the input of the element 4 delay. The output of the OR circuit is connected to the input of the control key on the transistor 1, and the output of the AND circuit to the key input on the transistor 2.

Timing diagrams explaining the cascade operation are shown in FIG. 2, where f / in is the input signal; f / sbix is the signal at the output of the 4-delay element; - signal on the base of transistor 1; C / B2 - signal at the base of the transistor 2.

 It can be seen from the diagram that the positive edge of the signal f / 6i coincides with the positive edge of the signal i / Bx. The positive front of the UQZ signal coincides with the positive front of the C / O signal, and the negative front with the negative front of the signal

t / BXThe drive current through transistors 2 and 3 is absent when the conditions

3;

uh, gkikl

Where

-1- and

33

delay of positive and negative fronts of element1M 4 delay (in

General case 7} The elimination of the through current at switching on is achieved due to the delay of the start time of turning on the 2T2 transistor relative to the start time of turning on the 1T1 transistor, which compensates for the unfavorable switch-on times.

The elimination of the through current when turned off is achieved due to a delay in the switching off time of the transistor 1 t; 1 off relative to the start time of turning off the transistor 2 compensating unfavorable scatter time.

Subject invention

An output stage containing a control and output transistor switches connected according to a common emitter circuit and an emitter follower whose output is connected to the collector of the output switch transistor and the input to the output of the control key, in order to eliminate the through current , And “OR” schemes and a delay element, the output of which is connected to the inputs of the said AND and “OR” circuits, the second inputs of which are combined with the input of the delay element, and the outputs are connected to the inputs of the control and output switches naturally.