KR19990049424A - Low Current High Speed Switching Circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low current high speed switching circuit, comprising: a first latch for synchronizing input data with a clock; First and second level shifts for receiving second and third latches, and outputting the second and third latches, respectively, and outputting bias data having a constant voltage whose voltage value is not "0"; Current switches in the current switch continuously eliminate the gate delay caused by the first latch in the second and third latches by configuring the current switches to receive the output of the second level shift as the bias voltage and output the current as the output. Glitch noise generated when using digital logic can be reduced by outputting to This is to reduce the switching time.

Description

Low Current High Speed Switching Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low current high speed switching circuit, and in particular, to reduce glitch noise generated when using digital logic in a current switching circuit of a digital to analog converter. The present invention relates to a low current high speed switching circuit capable of high speed switching with low current.

In general, digital to analog converters are already well-suited to changing information by a quantity (digital quantity) consisting of a combination of input codes or numbers into a continuous quantity (analog quantity) such as the position of an object or the magnitude of a voltage. It is a known fact.

In addition, the digital-to-analog converter requires a reference voltage, an operational amplifier, a latch, and a logic circuit necessary for inputting data. The logic circuit is configured by an electronic switch and controlled by a digital switch.

The digital switch includes a latch 1 for synchronizing data Data with a clock CLK, as shown in FIG.

A differential amplifier 2 for outputting a differential output Do1 (Do2) by comparing the synchronized data Do, which is an output of the latch 1, with a reference voltage Vref;

Consists of a current switch (3) for receiving a differential output (Do1) (Do2) output from the differential amplifier (2) to selectively output a current value,

The clock CLK is inputted to the clock terminal CK of the latch 1 in which data Data is input to the input terminal D to synchronize the data Data with the clock CLK.

The current I1 is applied to the source of the transistors FET1 and FET2 of the differential amplifier 2, in which the data Do and the reference voltage Vref, which are synchronized with the clock CLK, are respectively input to the gate at the latch 1. To be detected,

The driving power supply VDD is supplied to the gate and the drain of the transistors FET3 and FE4 at the same time so that the differential output Do1 and Do2 are outputted at the contact point whose source is connected to the drain of the transistors FET1 and FET2. Make sure,

The bias currents IQ1bias and IQ2bias are supplied to the drains of the transistors FET5 and FET6 of the current switch 3 to which the differential outputs Do1 and Do2 are applied to the gates so that the currents in the common connected source I2) is configured to be output.

However, according to the conventional digital switch as described above, the latch 1 receiving the data DATA outputs the data Do synchronized with the clock CLK, and the differential amplifier 2 receiving the data Do is received. ), The differential output (Do1) (Do2) was output as a bias current while comparing the reference voltage (Vref), so that the current is output from the next current switch (3), so that the digital / analog converter can operate at high speed. Switching must be made, and at this time, since the bias current I1 of the differential amplifier 2 must be increased, a large current must be supplied.

Accordingly, the present invention provides a low current high speed switching circuit that can reduce the glitch noise generated when the digital logic is used in the current switching circuit of the digital / analog converter and the switching time when switching the current with a small current. It is for that purpose.

The present invention for achieving the above object is a first latch for synchronizing the input data to the clock,

A second latch receiving data synchronized with a clock from the first latch and synchronizing with an inverted clock;

A third latch for receiving data in synchronization with a clock in the first latch and inverting the inverted clock;

First and second level shifts receiving the outputs of the second and third latches, respectively, and outputting bias data having a constant voltage whose voltage value is not "0";

By configuring the current switches to receive the output of the first and second level shifts as a bias voltage and output the current as the output continuously, the glitch noise generated when the digital logic is used can be reduced and with a small current. The switching time can be reduced when switching the current.

1 is a circuit diagram showing the configuration of a conventional digital switch.

2 is a circuit diagram showing a configuration according to an embodiment of the present invention.

Figure 3 is a waveform diagram of the main part showing the operation of the present invention.

Explanation of symbols on the main parts of the drawings

11: first latch 12, 14: inverter

13: second latch 15: third latch

16: first level shift 17: second level shift

Figure 2 shows the overall configuration according to an embodiment of the present invention,

A first latch 11 for synchronizing with the clock CLK supplied to the clock terminal while receiving input data Data at the input terminal;

The clock inputted to the clock terminal is inverted by the inverter 12 while receiving the data Do1 synchronized to the clock from the first latch 11 to the input terminal ( A second latch 13 for outputting data Do2 synchronized with

Data synchronized to the clock in the first latch 11 and inverted by the inverter 14 ( ) Is supplied to the clock stage while receiving the inverted clock ( A third latch 15 for outputting data Do3 synchronized with

A first level shift 16 for outputting bias data Do4 of a constant voltage whose voltage value is not "0" by the bias voltage bias while receiving data Do2 which is an output of the second latch 13; ,

A second level shift 17 for outputting bias data Do5 of a constant voltage whose voltage value is not " 0 " by the bias voltage bias while receiving data that is the output of the third latch 13;

A first current switch 18 which receives the bias data Do4 which is the output of the first level shift 16 as a bias voltage and outputs the current which is the output;

The second current switch 19 is configured to receive the bias data Do5, which is the output of the second level shift 17, as a bias voltage and output an output current.

Referring to the operation state of the present invention configured as described above are as follows.

The first latch 11 that receives the data CL as shown in FIG. 3A while receiving the data Data as shown in FIG. 3C as an input terminal is input. The data Do1, which synchronizes the data Data with the falling edge of the clock CLK, is output as shown in FIG.

A clock as shown in FIG. 3B of FIG. 3 inverted by the inverter 12 while receiving data Do1 synchronized with the clock from the first latch 11 to the input terminal ( In the second latch 13 receiving the clock stage, the data Do1 synchronized with the clock is inverted. The data Do2, which is synchronized again with the falling edge of (), is output as shown in FIG.

Data as shown in FIG. 3E, synchronized with the clock in the first latch 11 and inverted by the inverter 14 ( ) Is the inverted clock ( ), The third latch 15 receiving the clock terminal is inverted after synchronizing with the clock ( ) Is the inverted clock ( The data (Do3) synchronized with the falling edge of () is output as shown in FIG.

In the first level shift 16 which receives the bias voltage bias while receiving the data Do2, which is the output of the second latch 13, the bias data Do4 having a constant voltage other than the zero value is removed. By outputting to the gate of the FET which is one current switch 18, the bias current IQ3bias supplied to the drain thereof flows to the current I through a common connected source.

In the second level shift 17 in which the bias voltage is supplied while receiving data, which is the output of the third latch 13, the bias current Do5 of a constant voltage, whose voltage value is not "0", is input to the first current switch. By outputting to the gate of the FET (18), the bias current IQ4bias supplied to the drain thereof flows to the current I through a common connected source.

Therefore, the low current high speed switching circuit of the present invention synchronizes the input data to the clock, the data synchronized with the clock directly or through an inverter, and synchronizes the inverted clock. By outputting bias data, the current is continuously output from the current switch while eliminating the gate delay caused when only one latch is used, thereby reducing the glitch noise generated when the digital logic is used. The switching time can be reduced when switching.

Claims (3)

In a low current high speed switching circuit in which input data is synchronized with a clock by a first latch, and then a current which is an output from a current switch receiving the bias voltage is output. Latch means for receiving data synchronized with the clock from the latch directly or inverted to synchronize the clock; And level shifting means for receiving the output of the latching means, respectively, and outputting bias data having a constant voltage other than "0" to the current switch. The method of claim 1, wherein the latch means comprises: a second latch receiving data synchronized with a clock from the first latch to an input terminal and outputting the data synchronized with a clock inverted by an inverter and input to a clock terminal; And a third latch configured to output data synchronized with a clock in the first latch and inverted by an inverter to an input terminal, and output the data synchronized with an inverted clock supplied to a clock terminal. The method of claim 1, wherein the level shifting means comprises: a first level shift for outputting bias data of a constant voltage whose voltage value is not "0" by a bias voltage while receiving data that is an output of the second latch; And a second level shift configured to output bias data of a constant voltage whose voltage value is not "0" by a bias voltage while receiving data, which is the output of the third latch, respectively.