SU443382A1 - Uniform computing environment - Google Patents

Description

This invention relates to the field of computational technology.

Homogeneous computing environments are known that contain a matrix of structurally redundant cells with tunable functional blocks and blocks of rearrangement of cells by the number of rows of the matrix, each of which contains registers and a switch, whose inputs are connected to the outputs of registers.

A common drawback of known homogeneous computing environments is the relatively low functional reliability.

In the proposed homogeneous computing environment, this disadvantage is largely eliminated.

This is achieved by the fact that each cell of the computing environment contains additional prohibiting schemes, an anti-matching circuit, and an isolation diode. The output of the malfunction indicator of the functional block. Each cell of the f-th row of the matrix is connected to the input of an additional anti-coincidence circuit of the same cell and through a separating diode connected to the f-th fault indication level connected to the inputs of the additional anti-coincidence circuits of all cells of the i-th row of the matrix and the control input of the switch unit for rebuilding the cells of the same row. The output of the additional anti-matching circuit of each cell is connected to the inputs of all additional

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prohibition circuits of the same cell, the outputs of which are connected to the control inputs of the tunable functional block of the cell. The second inputs of the / -th additional barring schemes for all i-fi cells of the matrix row are connected to the / / m output of the switch of the cell rearrangement block of the same row. The last output of the switch is connected to the indication of unrecoverable failures.

A block diagram of a homogeneous computing environment is shown in the drawing.

To simplify the description of the process of setting up functional units of the iia environment, the implementation of a given function and the process of rebuilding the environment when faults appear in the drawing do not indicate the functional relationships between cells, but only those used in the process of tuning and rebuilding.

The homogeneous computing environment is

from the structurally redundant cells united into the matrix, each of which includes a tunable functional unit 2, executed, for example, in the form of a logically stable network of multifunctional elements with code reorganization of logic, prohibition scheme 3 and matching circuit 4.

Each row 5 of the matrix of cells 1 includes a block 6 of the restructuring of the cells, consisting of the storage tuning codes for

tuning blocks 2 registers 7 (according to the number of tuning cycles) necessary to ensure the logical stability of the network from the multifunctional elements of the tunable function block 2 of any cell 1 line 5 in the class of implemented functions, and the switch 8 register outputs 7. The outputs 9 of each register 7 are connected to the input switch 10 of switch 8, and inputs 11 of registers 7 are connected to output memory buses of the tuning codes of functions implemented by cells 1 of a homogeneous computing environment.

Each of the outputs 12 of the switch 8 is connected to the functional input 13 of one of the prohibition schemes 3 of each cell 1 of the corresponding line 5 of a homogeneous environment. The control inputs 14 of the inhibit circuit 3 of each cell 1 are connected in parallel and connected to the output 15 of the anti-matching circuit 4, the control input 16 of which is connected to the output 17 of the malfunction indicator of the functional unit 2.

Functional input 18 of each anti-match 4 circuit is connected to the bus 19 of the fault indication of the corresponding row 5 of the matrix. Bus 19 of each row is connected to separation diodes 20 with outputs 1 / of failure indicators of tunable function blocks 2 of this row and connected to control input 21 of the corresponding switch 8, and outputs 22 of the inhibit circuits 3 of each cell 1 are connected to control inputs 23 of the corresponding-tunable functional block 2.

The signals arriving at the control inputs 23 of the function block 2 configure it for the implementation of a given function.

The output 24 of the switch 8 line 5 is connected to the terminal 25 of the indication of non-recoverable failures.

If before starting all the cells 1 of the homogeneous computing environment are in good condition, then the process of setting up any line 5 to be implemented by an arbitrariness from the class of functions implemented is as follows.

In registers 7 of block 6 of adjustment of cells 1 of each line from the storage device, tuning codes are entered that provide tuning to the specified function in the whole range of logical stability of networks from multifunctional elements of tunable functional blocks 2 of the corresponding line 5 of a homogeneous computing environment. The tuning codes from the outputs 9 of registers 7 are fed to the inputs 10 of switch 8, which passes to outputs 12 only the code from the first register 7. The first register is the one that stores the tuning code that ensures the logical stability of the functional blocks 2 to the maximum number of failures compensated for one setup code. The next in order registers 7 contain setup codes that provide the decreasing ability of function block 2 to compensate for failures. In this case, the set of all tuning codes provides compensation in 5 function block 2 of all possible failures. Setup codes from the outputs of 12 switches 8 are fed to the functional inputs (13 prohibition schemes 3 of each cell 1 of the corresponding row 5 of the computational

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Due to the fact that cells 1, as agreed, are in good condition, there are no signals from the outputs 17 of the malfunction indicators of the functional blocks 2 and there are no fault lines on the bus 19 for each line, and to the control 16 and 18 functional inputs anti-matching circuitry 4, the potentials are zero. This causes the absence of signals at the outputs 15 of the atits0-drop 4 and at the control inputs 14 of the inhibit circuits 3. Signals arriving at the functional inputs 13 of the forbidding circuits 3 are freely passed to the control inputs 23 of the tunable functional blocks 2

5 cells of each row 5 and each block 2 is configured to configure the corresponding line for the implementation of a given function.

Cells of the same computational environment configured in this way function without logical restructuring until a failure occurs in one of the cells, which can be detected depending on the principle of building the environment or hardware

5 control system, or using a test control.

If a malfunction is detected in the function block 2, line 5, leading to a distortion of the output signal, the output 17

0 of the corresponding fault indicator on the Wits fault signal. This signal is fed to the control input 16 of the corresponding anti-sweep circuit 4 and, passing through the separation diode 20, will go to the bus 19

5 of the failure indications of the corresponding row 5, the functional inputs 18 of all anti-sweep circuits 4 of this row and the control input 21 of the switch 8. On this signal, the switch 8 polls the next order register 7, and its outputs 12 receive the next setup code, which passes to the functional inputs of the 13 prohibition schemes for 3 of all the cells 1 of this line 5. Prohibition schemes for serviceable cells of this line

5 are locked, so the tuning code signals arriving at the functional inputs 13 of the inhibit circuits of 3 healthy cells do not pass to the control inputs 23 of the tunable function blocks 2 of these cells and

The zero is produced by logical adjustment of these blocks. The logical rearrangement of the functional unit 2 occurs only in the cell in which the malfunction appears, leading to a distortion of the output signal, since only in this cell the inhibitor 3 circuits are open. This ends the first cycle of adjustment.

If, after the first cycle of restructuring, a failure is compensated for by a logical network restructuring of the multifunctional elements in the functional unit 2 of defective cell 1, then the signal at the output 17 of the malfunction indicator of the functional unit 2 of this cell is absent. This causes a signal at the output 15 of the corresponding antasapad 4 circuit (in the presence of a single signal in the bus 19 to indicate failure of this line 5), which goes to the control inputs 14 of the prohibition circuit 3 and locks the circuit of the cell under consideration, which makes it impossible multifunctional elements of the corresponding functional unit 2 in the subsequent cycles of the restructuring process.

The presence of a single signal in the bus 19 of the indication of failures of the corresponding line 5 after the end of the first cycle of adjustment indicates that there is a cell in this line, remaining with a faulty after the first adjustment loop. In this connection, the second cycle of adjustment begins.

On a signal coming to the control input 21 of switch 8 via the bus 19 of the corresponding line, switch 8 prepares the next register 7, and signals of the next setup code appear at the outputs 12 of the switch that pass through the open inhibit patterns 3 of the remaining faulty cells 1 of this line and the logical reconstruction of the functional unit 2 of this cell is performed.

In the future, the second cycle of adjustment proceeds as before.

The restructuring process to compensate for the failure contains as many cycles as are required to restore the functioning of the failed cell. A sign of the end of the restructuring (restoration of the failed cell) is the absence of signals in the fault indication bus 19.

The proposed restructuring method provides the ability to simultaneously eliminate failures in several cells of one or several rows of a homogeneous computing environment. If the failed functioning of the failed cells 1 of any line 5 is not restored after they have been reconfigured by the tuning code stored in the last register 7 of the block b of this line, then on the terminal 25 of the display there are no recoverable

failures of the corresponding switch 8 by a Wits non-recoverable failure signal.

Subject invention

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A homogeneous computing environment containing a matrix of structurally redundant cells with tunable functional

blocks and rebuilding blocks of cells by the number of rows of the matrix, each of which contains registers and a switch, the inputs of which are connected to the outputs of registers, characterized in that with a c-gli increase functional reliability, each cell contains additional prohibition schemes, anti-coincidence circuit and separation the diode, the output of the malfunction indicator of the functional block of each cell of the t-th row of the matrix is connected to the input of an additional anti-coincidence circuit of the same cell and through the separation diode is connected to the i-th bus of the fault indication, Connected to the inputs of additional anti-matrices of all the cells of the t-th

matrix rows and to the control input of the switch of the cell rebuilding block of the same row, the output of the additional anti-coincidence circuit of each cell is connected to the inputs of all additional prohibition circuits of that

the same cells, the outputs of which are connected to the control inputs of a tunable functional block of the cell, the second inputs of the / -x additional prohibition schemes for all cells of the 1st row of the matrix are connected to the / -th output

switch unit rebuilding cells of the same line, the last output of the switch is connected to the indication terminal of unresponsive failures.

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