SU430023A1 - AUTOMATIC REGISTER REGULATOR - Google Patents

Description

one

This invention relates to the printing industry, in particular, to automatic register control systems in tape processing machines, for example rotary printing machines.

There is a known automatic register controller, in which register mismatch information is received on two inputs from a photoelectric sensor and a logic circuit is converted into a series of pulses. The duration of the series is proportional to the mismatch, and the frequency of the pulses depends on the speed of the web.

The pulses of this series are summed by a reversible counter. The operating time of the servomotor is equal to the reading time of the content of the reversible counter by pulses of the auxiliary generator a. The magnitude of the proportionality coefficient of such a transformation is equal to the ratio of the frequency of the read and write pulses. The mismatch sign is recorded and determines the direction of the corrective action. The specially formed signal returns the regulator circuit to the initial state. A web speed sensing device is a recording pulse generator that is operated simultaneously with the entire controller.

The disadvantage of the known regulator is that due to the large inertia of the section of the moving web and the effect of interference (roll beating, lateral vibrations of the web, slipping and wiping of the web, alternating moisture and temperature), it does not provide stable and stable control process.

The purpose of the invention is to increase the dynamic stability and speed of the control process.

For this, the proposed controller is equipped with a measurement cycle allocation unit connected to an input device generating a mismatch signal, which is a three-channel logic assembly of three matching circuits associated with the inputs of the corresponding binary dividers of the reversible counter, and the measurement cycle selection block is connected to matching schemes for recording resolution with appropriate coefficients. FIG. 1 shows the block diagram of the proposed controller; in fig. 2 is a circuit for measuring measurement cycles.

The controller contains a photoelectric sensor 1 register mismatch, which through the input device 2 and logic circuits

3-5 matches are connected to the inputs 6, 7 and 8 of the binary dividers of the reversing detector 9, respectively. The second output of the device 2 is connected to the inputs of the matching logic circuits 11 and 12 via the character storage circuit 10. The selector pulse sensor 13 is connected to the device 2 and the measuring cycle selection circuit 15 via the selection and cycling circuit 14, the outputs of which are connected to the second inputs of the matching circuit 3-5.

One output of the measurement cycle detection circuit 15 is connected to the mode control circuit 16. The web speed sensor 17 is connected to a write pulse generator 18, the output of which is connected to device 2.

A read pulse generator 19 is connected via a logic circuit 20 to a counter 9, the output of which is connected to a reset circuit 21. The output of the circuit 21 is connected to a counter 9, a cycle selection circuit 15 and a mode control circuit 16. One output of circuit 16 is connected to the third outputs of logic circuits 3-5, the second output of this circuit is connected to counter 9, and the third output is connected to the second input of logic coincidence circuit 20 and through logic circuits 11 and 12 coincidence and power amplifier 22 is connected to the executive engine 23.

The measurement loop allocation circuit 15 comprises a counter of 24 cycles consisting of a series of binary dividers, the outputs of which are connected to the inputs of a selector device 25 consisting of matching logic circuits 26, the outputs of which are connected to the inputs of a switching device 27 consisting of a series of switches into several positions and several logical assemblies 28. Each of them contains the same-named outputs from the switches.

The regulator works as follows.

From the sensor 1, via two channels, the device 2 receives information about the state of the register in the form of two pulses, corresponding to two check marks on the moving web. The shift between them corresponds to a register mismatch.

From the sensor 13 to the scheme 14 of the selection and cyclicity comes a dual pulse, synchronized with the passage in front of the sensor 1 check marks. The signal from circuit 14 blocks the operation of device 2 during the entire measurement cycle, except for the short time interval between two selector pulses.

Information about the speed of movement of the web comes from the sensor 17 to the generator 18 of recording pulses, which are continuously fed into the device 2.

In each measurement cycle, at the output of device 2, a series of pulses is formed, the duration of which is proportional to the register mismatch, and the frequency of the pulses is proportional to the speed of the web and

determined by the given sensitivity of the controller.

Thus, the register mismatch information is represented in digital form. The number of pulses in the series corresponds to the magnitude of the mismatch.

The mismatch mark is generated by the device 2 and is remembered by the circuit 10.

Register mismatch signal from output

devices 2, via logic circuits 3-5, coincidence flows into counter 9, where digitally represented mismatches are summed and accumulated over the required number of measurement cycles. The operation of the logic circuits 3–5 coincidences are also determined by the measurement cycle allocation circuits 15 and the mode control circuit 16.

The pulse from the circuit 14 in each measurement cycle is fed to the input of the circuit 15, which sets the value of the coefficient with which the error in this measurement cycle should be recorded in counter 9. At coefficients 1, 2 or 4, the recording of mismatches presented in digital form,

in the counter 9 through schemes 3-5, starting with 6, 7 or 8 binary dividers. With a factor O, the discrepancy record in this cycle of measurement does not occur. Scheme 15 also specifies the number of measurement cycles sufficient to implement the necessary control law.

In the last cycle, circuit 15 sends a pulse, which is converted by mode control circuit 16, to the command to transfer the controller from

the measurement mode in the register mismatch correction mode.

This command prohibits the circuits 3-5, and the counter 9 is reversed. The information recorded in it is now represented in reverse binary code. In the error correction mode, the prohibition is removed from the logic circuit 20 of coincidence, through which the content of the reversible counter is read by pulses from the generator; nineteen.

During readout time, circuit 11 or 12 is open, depending on the mismatch sign fixed by circuit 10. This determines the duration and direction

work of the executive engine 23 through the amplifier 22.

Upon completion of the readout, the circuit 21 generates a signal for resetting the initial state of the counter 9 and the circuit 15. The circuit 16 does not convert the controller to the write mode.

The coefficient of proportionality of the conversion of the proposed controller depends on the ratio of the frequency of the read and write pulses, the number of averaged mismatches and the magnitude of their coefficients, as well as the method of reading the information recorded in the counter 9. The read ratio depends on which binary divider counter 9 begins reading.

The counter 24 counts the pulses from the circuit 14 corresponding to each measurement cycle. Based on the information from the counter 24, the selector device 25 allows a signal from the corresponding logic circuit 26 to match the counter to the register 9 in the required measurement cycle. The positions of the switches corresponding to each measurement cycle determine the magnitude of the mismatch recording factor in that cycle. Logic assemblies 28 combine loops with the same write coefficients and control the operation of logic circuits 3-5 matches. In the last measurement cycle, the counter 24 outputs a write end signal to the circuit 16. The signal from the circuit 12 returns the counter 24 to the initial state.

Subject invention

Automatic register controller containing photoelectric error sensor, selector pulse sensor, date1; web speed, input device that generates the error signal in digital form, sign storage circuit, selection signal forming circuit and input cycle signal, reversible counter, generators write and read pulses, control circuits and the executive authority, characterized in

that, in order to increase the dynamic stability and speed of the adjustment process, it is equipped with a measurement cycle allocation unit connected to an input device generating a mismatch signal, which is a three-channel logical assembly of three matching schemes associated with the inputs of the corresponding binary dividers of the reversible counter at the same time the block of allocation of cycles of measurement

connected to match schemes to enable recording with the corresponding coefficients.