SU422016A1 - DEVICE FOR REGISTRATION OF SEQUENTIAL PROCESSES - Google Patents

Description

one

The invention can be used, in particular, to collect data (temporal and accuracy characteristics) when the dispatcher works behind control panels of complex technological installations.

There are known devices for registering time processes in centralized control systems that contain counters, a current time counter, a reference frequency generator connected to the counter inputs, an output matching unit and a registration unit, the input start-stop bus of the counters are connected to the controlled points of the object through an input switch the block, and the outputs of the meters are connected via an output matching unit to the registration unit.

Such a device allows centralized data collection (temporal characteristics), for example, when controlling the dispatcher of complex process units. However, the set of work program algorithms. Research (connection of the corresponding points of the object to the working buses of the device) is performed manually using the switches of the input switch.

In addition, there is no control over the erroneous operations of the dispatcher, as well as control over the failure of the dispatcher to perform the necessary operations for the maximum set time.

The purpose of the invention is to expand the functionality of the device and increase its efficiency.

The goal is achieved by introducing address registers, comparison circuits, an additional OR circuit, separation diodes, an address allocator, input and output encoders, whose inputs are associated with the start and stop signals of the object being monitored, respectively, and the information output of the encoder input is connected to the first inputs

address registers, the clock output of the input encoder is connected to one of the inputs of the address distributor, the outputs of the cells of which are connected respectively to the second inputs of the counters and to the write resolution buses

address registers, the first code outputs of which are connected to the second output of the output matching unit, and the second ones are connected respectively to the first inputs of the comparison circuits, the outputs associated with the third

the inputs of the corresponding counters, through the OR circuit with the third input of the output matching unit and through the separation diodes with the write-off buses of the corresponding address registers and with the inputs of the address distributor cells.

The overflow outputs of the counters are connected to the counter discharge buses, respectively, through separation diodes to the write-off buses of the corresponding address registers, to the inputs of the address distributor cells and through the additional OR circuit to the fourth input of the output matching unit, the information output of the output encoder is connected to the second inputs of the comparison circuits and to the fifth input of the output coi aa block, and the second output of the output matching block is connected to the second input of the current time counter.

The drawing shows a block diagram of the device. It contains input coder 1, output coder 2, address registers 3, address allocator 4, counters 5, reference frequency generator 6, comparison circuits 7, output matching block 8, separation diodes 9 and 10, OR 11 12 circuits, current time counter 13 and the registration unit 14.

The device works as follows. When a start-pulse arrives from any controlled point of an object (for example, from a controlled point whose sequence number is 25), a corresponding code is formed at the corresponding input of the encoder / in the latter and in parallel arrives at the code inputs of the address registers 3. Simultaneously from the clock output of the shifter / enters the starting pulse to the address allocator 4, with which the first cell is triggered and sends a pulse to the resolution resolution bar of the first address register 5 and to the corresponding input of the counter 5, and goes to state "1" and prepares the communication circuit of the second cell of the address distributor 4 with the second address register 3. As a result, the number of the control point of the object is recorded in the first address register 3, the counter 5 is started, the counting pulses from the reference frequency generator start at its input 6. In turn, the address register 3 prepares (for the first code inputs) with it the associated circuit of equilibrium 7.

When the next start-pulse arrives from the controlled point, for example, the sequence number is 46, the corresponding input of the input encoder 1 is similarly recorded in the second address register 3 and the associated counter 5 is switched on with it.

In this case, the second cell in the address allocator 4 enters the state “b” and prepares the communication circuit of the third cell with the third address register 3, etc.

Upon receipt of a stop pulse, for example, from the checkpoint N ° 25, a corresponding code is formed at the corresponding input of the output encoder 2, and from the output of the encoder in parallel it goes to the second code inputs of the comparison circuits 7 and to the input of the output matching unit 8.

In this case, in the comparison circuit 7 associated with the first address register 3, the codes will coincide. The impulse coincides with the output of the comparison circuit 7 parallel5 but is fed to another input of counter 5, through separation diode 9 to the write-off bus of address register 3, to the input of the first cell of the address allocator 4 and through the scheme "OR 11 to the input of output matching 10 of block 8.

At the same time, in the output matching block, the code “Positively evaluating the operation; In addition, the counter 5 stops and information (measured time interval) from its output, as well as information (reference point number) from the address register 3 n from the output terminal 2 (the number of the same coitrol point) are sent to the corresponding inputs of the output matching unit 8 From the clock output of the output matching unit 8, the starting pulse enters the current time counter 13. As a result, information (time interval relative to the start of work) from the current counter, 5 times 13 and from the output matching unit 8 to the no. enters to the registration unit 14, which documents the positive assessment of the operation (determined by the code), the number of the control point of the object (from the first 0 address register 3), the value of the time interval of the operation (from counter 5) and the time interval value relative to the beginning work or previous operation (from the current time meter 13). At the moment of retrieving information into the registration unit M, the counter 5, the first address register 3 and the first cell in the address allocator 4 are brought to the state of the reset pulse. At the same time, the first address repistor 3 is again ready for receiving (recording) new information.

When the operator performs an "erroneous operation, i.e. when the stop pulse arrives at the input of the tweeter 2 outputs from the control point of an object whose number is not recorded in 5 address registers 3, the information (the number of this control point of the object) from the output of the output encoder 2 is similar the previous one goes in parallel to the second inputs of the comparison circuits 7 and to the input of the output matching unit 8. In this case, the comparison circuits 7 do not match the codes, since the number of this control point of the object was not recorded in the address registers. As a result, the impulse of coincidence 5 does not arrive at the output matching block 8, which causes the formation of a " Negatively Operator Operational Assessment code. At the same time, from the output matching unit 8, a starting pulse enters the current time counter / 5, and the information from its output and current time counter 13 enters in parallel to the registration unit 14.

As a result, the registration unit 14 documents the negative evaluation of the operator’s operation (as defined by the code),

the control point of the object (from the output encoder 2) and the value of the time interval relative to the start of work or the previous operation (from the current time counter 13).

If the operator fails to perform the corresponding operation, for example, on a command whose deadline is recorded in the second address register 3, when the time limit for the operation expires, counter 5 overflows.

In this case, an overflow pulse from the output of the last cell of the final decade of counter 5 is fed to the reset bus of the meter 5 itself and through the separation diode 70- to the bus of the address register 3, to the input of the second cell of the address distributor 4, and through the OR 12 circuit to the input output matching block 8.

As a result, in the output matching block 8 a code is generated that is not executed by the operator. From the output matching unit 8, a starting impulse arrives at the current time counter 13, and the information from the output of unit 8 and from the output of the current time counter 13 in parallel enters the registration unit 14.

As a result, the registration unit documents the operator’s failure to perform the operation (as defined by the code), the checkpoint number (in this case No. 46 from the second address register 3), and the time interval value in relation to the start of work or the previous operation (from the current time counter 13). With the output of information to the registration unit 14, the address register 3 is released and ready to receive (write) the new information.

Subject invention

A device for registering sequential processes, comprising a reference frequency generator connected to the first input of the current time counter and to the first

the inputs of the corresponding counters, the information outputs of which are connected through the first input of the output matching unit to the first input of the registration block, to the second input of which the current time counter output and the "HLR" circuit are connected, in order to expand the functional capabilities of the device, address registers, we compare,

additional scheme “OR, isolation diodes, address allocator, input and output encoders, inputs of which are connected with start and stop signal buses of control points of the object, respectively, and the information output of the input encoder is connected to the first inputs of the address registers, the input clock of the input encoder is connected to one of the inputs of the address allocator, the outputs of the cells of which are connected respectively to the second high-speed counters and to the buses for writing address registers, the first code outputs of which are connected They are connected to the second input of the output matching unit, and the second ones are connected to the first inputs of the comparison circuits, the outputs connected to the third inlet outputs of the corresponding counters, through the OR circuit to the third input of the output matching unit and through the separation diodes to the buses

writing off the corresponding address registers and with the inputs of the address allocator cells, the overflow outputs of the counters are connected to the meter reset buses, respectively, through isolation diodes - to the buses

writing off the corresponding address registers to the inputs of the address allocator cells and through the additional OR circuit to the fourth input of the output matching unit, the information output of the output encoder is connected to the second inputs of the comparison circuits and to the fifth input of the output matching unit connected to the second input of the current time counter.

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