Б. С. Данилов Л. Г. Израильсон В. Б. Садовский С. В. Стукалов Ю. А. Тамм
Б. С. Данилов
Л. Г. Израильсон
В. Б. Садовский
С. В. Стукалов
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А. Тамм Ю.
Б. С. Данилов
Л. Г. Израильсон
В. Б. Садовский
С. В. Стукалов
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Application filed by А. Тамм Ю., Б. С. Данилов, Л. Г. Израильсон, В. Б. Садовский, С. В. СтукаловfiledCriticalА. Тамм Ю.
Priority to SU1745943ApriorityCriticalpatent/SU412685A1/ru
Application grantedgrantedCritical
Publication of SU412685A3publicationCriticalpatent/SU412685A3/ru
Publication of SU412685A1publicationCriticalpatent/SU412685A1/ru
Process and circuit arrangement for the measuring of the frequency of bit erros and block errors with optional block length in the transmission of binary coded data characters