SU379979A1 - ALL-UNION - Google Patents

Description

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This invention relates to analog converters.

Voltage converters in a code with a self-monitoring and auto-zero zero system are known, containing a zero-body, a code-voltage converter, a register, keys, triggers, AND, OR, NOT circuits.

A disadvantage of the known devices is the conversion error due to the component of the response threshold, the magnitude of the voltages being triggered, and also insufficient. accurate reliability due to gradual changes in the operating parameters of the null-organ circuit.

The proposed device differs from the known ones in that the first input of the first key is connected to the output of the source of the voltage being converted and the first input of the second key, the second input of which is connected to the output of the converter - the voltage and the second input of the first key, the third and fourth inputs of the keys are connected with the release of the first trigger, and the outputs of the keys are connected to the corresponding inputs of the null organ. The output of the zero-organ is connected to the input of the first circuit “And through the circuit“ is NOT connected to the inputs of the second and third circuits “I. Other inputs of the circuits “And connected to the output of the first circuit“ OR The output of the first circuit “AND through the fourth circuit“ AND is connected to the second input of the second trigger, the first input of the second circuit “OR and the input of the fifth circuit“ AND, and through the sixth circuit to the second input of the second circuit “OR and the first input of the third“ OR . The control inputs of the fourth and sixth circuits “And connected to the output of the third trigger, V1khod which is connected to the output of the second circuit“ And the input of the seventh circuit “I. The control input of the latter is connected to the output of the second trigger, the other output of which is connected to the control input of the third "I. The output of the third circuit "AND connected to the second input of the third circuit" OR and the first input of the fourth circuit "OR, the second input of which is connected to the output of the seventh circuit" And the input of the eighth circuit "I. The output of the eighth circuit “AND” and the output of the fifth circuit “AND are connected to the inputs of the fifth circuit“ OR.

The block diagram of the proposed device is shown in the drawing.

The converter consists of register /, converter code - voltage 2, keys 3 and 4, zero-body 5, schemes "OR 6-10, schemes" AND 11-18, schemes "NOT 19 and triggers 20-22 (not in the drawing control scheme is given).

The principle of operation of the device is based on the following.

Upon completion of the conversion, the register / has a binary code equivalent to the voltage oc ± Op ± A ± 2, where Nose is the feedback, coupling voltage;

(TP - the maximum value of α-absolute error;

 - the value of the converter error due to the presence of a trigger threshold in the null organ;

li is the overcompensation voltage;

/ 2 - component of the operation threshold, caused by the dependence of the operation conditions on the values of the compared voltages. By switching the control circuit, channels ix and Nose to the inputs of the null organ, we will have voltage f / oczfc: an ± Af ± on one input, and on the other input .Uix- By analyzing the signal at the output of the null organ in / С cycles, necessary for the auto-correction of the code, on the register / we obtain a code equivalent to the voltage Loo ± cTn ± Ai ± i ± 2- The arithmetic average of the binary codes received by the converter per cycles and, cycles, will give a binary code equivalent to the voltage f / oo ± an.

Consider the operation of the device in three possible cases.

1. At the end of the transformation, the zero-organ 5 sbala.nsirovan, in view of the supposed equality of the voltages at its inputs. In () -, th tact, the control circuit: outputs a polling signal of the register /, which is able to operate in the reversible counter mode, and sets the trigger 20 to a single position. Thus, the keys 3 vi 4 switch the Hix and Nose Hia channels to the second and first zero-organ input, respectively. In this case, there are three options.

In the first case, the zero-body is balanced, due to the supposed equality of the stresses at its inputs. In the (l- | -2) th cycle, the signal through the circuits 6, 12, 16, 8 enters the lower register register 1 of the converter, reducing its number by one unit of the lower order. At the same time, the trigger 21 is set to a single position. Decreasing the number in the register changes the value of the voltage t / i at the zero organ 5. This creates an imbalance, since a signal appears at the output of the null organ, which by means of circuits 11, 13, 9 V, (n + 3 ) -OM tick enters the register, increasing its number by "1 youngest bit. At the same time, an auto-correction termination signal of the received binary code is generated. In the case when the action of the system of self-control and auto-correction is similar to the case described above. In this case, the decrease in the number in register 1 occurs until a signal appears at the output of the zero-body 5, which will lead to an increase in its number by a unit of the least significant bit. If .In the (“+2) -th cycle, the signal through the circuits 6, 11, 14, 9 enters the low-order bit of the register / transform-atel, increasing its number by one unit of the low-order bit. At the same time, the trigger 22 is set to a single position. At the same time, an increase in the number in the register / occurs as long as there is a signal at the output of the null organ 5. As soon as the zero-organ 5 is balanced, the output signal will disappear and the control signal of the circuit 6, 15, 8 will go to the lower section of register 1 of the converter 2, reducing its number by one unit of the lower order. At the same time, an auto-correction termination signal of the received binary code is generated.

2. The null body 5 is unbalanced at the end of the transformation due to the fact that. In (n -) - oi tact, the control circuit generates a polling signal of the register / converter 2 and simultaneously sets the trigger 20 to the single position. Thus, keys 3 and 4 switch channels f / GJ and L / oc to the second and first inputs of the null organ, respectively. Three options / fi 2,, are possible for which the operation of the self-control and auto-correction scheme is similar to the cases described above.

3. This option is reduced to the first two in connection with the fact that with it the null organ 5 produces a signal leading to a decrease in the number in the register.

If the existing K. additional ticks are insufficient for correcting the received code, then the system of self-control and auto-correction in () -OM tick through the circuits 17, 18, 10 generates an error signal.

Subject invention

Voltage converter in the code with the system of self-control and zero auto-correction, containing a zero-body, converter code-voltage, register, keys, trigger circuit AND, OR, NOT, characterized in that, in order to eliminate the error due to component the triggering threshold caused by the dependence of the conditions of a campaign on the values of the compared stresses, and also due to gradual changes in the operating parameters of the zero-organ circuit, in it the first input of the first key is connected to the output of the source to be transformed and the first input the second key, the second input of which is connected to the output of the converter, the voltage code and the second input of the first key, the third: and the fourth key inputs are connected to the output of the first trigger, and the key outputs are connected to the corresponding inputs of the zero body, the output of the last is connected to the input the first circuit “And and through the circuit“ is NOT connected to the inputs of the second and third circuit “And, the other inputs of the circuit“ And connected to the output of the first circuit “OR, the output of the first circuit“ And respectively through the fourth circuit “And connected to the input of the second trigger, trans the second input of the second OR circuit and the sixth AND circuit is connected to the second input of the second OR circuit and the first input of the third OR circuit, while the control inputs of the fourth and sixth AND circuit are connected to the output The third trigger, whose input is connected to the output of the second AND circuit and the input of the seventh AND circuit, the control input of the latter is connected to the output of the second trigger, the other output of which is connected to the control input of the third And circuit, the output of the latter is connected to the second input of the third circuit "OR and the first entrance is thurs rtoy circuit "OR, the second input of which is connected to the output of the seventh circuit" entry and eighth AND circuit "And, the last output and fifth scheme" and are connected to the inputs of the n "OR circuit.

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