SU377768A1 - COMPARATOR OF BINARY NUMBERS \ :: 0; -: OUYUSNAYA i; iATlliT ^ "T ^ l. ^ I; i" li ^ "A; - Google Patents

Description

The proposed device relates to the field of automation and computer technology and can be used in the implementation of technical means of digital automation and discrete computers.

A binary binary compiler is known that contains two 2n-bit registers and successively connected threshold elements. However, the known devices are complex and have a signal propagation time of about pt, where the t-delay of the signal is in one bit.

The proposed comparator differs from the known ones in that it uses n threshold elements with a threshold (+ 4) and five inputs, two of which have weights (+ 2) and the rest - (+ 1), direct outputs of each i-ro the bit of the first register (, 3 ... 2,, 1) and the inverse outputs of each of the same name of the second register are connected to two of the inputs with the weight of (+ 1) / th threshold element (, 2, ... n ), respectively, and the direct outputs of each (i + l) -ro bit of the first register and inverse outputs of each of the same name of the second register are connected to two other inputs with Som (H-2) of the same / -th threshold element, respectively: the fifth input of the first threshold element is connected to the pilot signal bus; the fifth inputs of all

the subsequent threshold elements are associated with the outputs of the previous ones: the output of the last threshold element is connected with the output bus of the device.

This simplifies the device and

increase its speed.

The drawing shows a block diagram of the proposed compiler,

It contains s-th threshold elemept

(li, lo, ... “) and two registers 2 and 3, designed to receive compared numbers. For every two bits of binary numbers being compared, one threshold element is used (PE), which has a threshold (+ 4) and

five inputs, two of which have weight (+ 2), and the other three have weight (+1). One of the inputs with weight (+ 2) is connected to the direct output of the trigger of this bit of the first number, the second input with weight (+ 2) is connected to the inverse output of the trigger of this bit of the second number, one of the inputs with weight (+ 1) is connected to the direct trigger output of the previous bit of the first number, the second input weighing (+ 1) is connected to

the inverse of the trigger output of the previous bit of the second number, and the third input with a weight (+ 1) is connected to the output of the previous threshold element.

The work of the proposed comparator consider an example. Obosait the first number through x, the second number through y control signal through T, and the output signal of the comparator through F.

Let L 5, and i / 4. This means X2 x ... x „0, Ou 1, Up 0 –Do Let T 0. In the first PE, two entrances with weights (+ 1) and one entrance with weights {+ 2 ). Since the sum of these weights is equal to the threshold, the element is excited, and at its output but is a signal. In the second PE, one input with a weight (+1) and one input with a weight (+ 2) are excited. Since the sum of these weights is less than the threshold, the element is not excited until the signal from the output of the previous PE arrives. With the arrival of this signal, the second PE is also excited. In subsequent PEs, the sum of the weights of the excited inputs is equal to (+ 3), so the output signal of the second PE alternately excites the next PEs, and a signal appears at the output. Thus, Г - О п F 1. Hence,, i.e., the initial position is confirmed:.

In other cases, the circuit works in an analolic manner. Obviously, in the proposed comparator, the propagation time of the cnnal from the first to the last discharge

/ g

equal to D - signal delay in one PE. Other things it is

the time is twice as small as the signal travel time in the known comparators.

Subject and item

A binary number comparator containing two 2n-bit registers of serially connected threshold elements, characterized in that, in order to increase the speed of the device and simplify it, the device contains n threshold elements with a threshold (+4) and five inputs, two of which have weights (+ 2), and the rest- (+1); the direct outputs of each t-ro bit of the first register (, 3 ... 2p-) and the inverse outputs of each bit of the same name of the second register are connected to two of the inputs with a weight (+1) / -th of the normal element (j 1, 2, ... ,,) matches, and the direct outputs of each ((+ 1) -th digit of the first register and the inverse outputs of each homogeneous discharge of the second register are connected to two other inputs with a weight (+ 2) of the same / - The threshold element corresponds to the type; the first input of the first threshold element is associated with the thickness of the control signal, and the new inputs of all and subsequent thresholds These elements are connected to the outputs of the previous ones, and the output of the last threshold element is connected to the output device.