SU375680A1 - PERMANENT STORAGE DEVICE - Google Patents

Description

The proposed device can be used in computing.

A permanent storage device (ROM) is known, containing two identical duplicate blocks in each other's work, the same outputs of which are connected according to the “OR” scheme, and each block has an address part, a drive with “-address buses, bit amplifiers, local control. In this case, the scheme of each ROM block is made so that the occurrence of false “1 binary information at any output of the block in the event of a catastrophic failure of details, the event is less likely than the occurrence of false“ O.

The purpose of the invention is to reduce the equipment of the device.

This is achieved by the fact that the i-address field of the first accumulator is connected in series with the (n - 1) -th address field of the second accumulator and with the t-M output of the address block. The gating bus of the bit amplifiers of the first accumulator is associated with the output of the first cycle of local control unit ROM, and the gating level of the bit amplifiers of the second drive with the output of the second cycle of local block of ROM control.

This makes it possible to exclude equipment equivalent to the address part of one

unit without reducing the reliability of the device as a whole.

P1a drawing shows a functional diagram of a permanent storage device.

The / -I target area / first accumulator 2 is connected to (n - 1) -th address width 3 of the second accumulator 4, for example, in series, and these lengths are connected to the output address driver 5 of the address part 6

first block; the output 7 of this former serves as the tM output of the address part 6. The outputs 8 of the accumulators are connected to their bit amplifiers 9, the same outputs 10 of the amplifiers 9 are connected to the circuit OR 11. The 12 strobe bus 12 of the amplifiers 9 of the first accumulator 2 is connected to the output 13 the first cycle of treatment of the local ROM control unit 14, and the bus 15 for gating the bit amplifiers 9 of the second drive

4 - with the output 16 of the second cycle of treatment of the local control unit. The scheme works as follows. Appeal to the ROM for the desired information occurs in two cycles. In the first tact address

the required information is fed to the address rails 17, in accordance with which, for example, the i-th output of the address part 6 is excited. At the outputs 8 of the first drive 2, signals corresponding to the information

i-th address area, and on outputs 8 of the second

drive 4-- (n - i) -H address bus. In the first cycle, the reference signal is fed only to the input 18 of the first cycle of the local control unit ROM, the strobe signal to the discharge amplifiers 9 of the first accumulator 2. As a result, only the first accumulator is supplied to the OR circuit. From the output of the circuit “OR signal passes to the single input of the trigger 19 register numbers.

In the second cycle of the call, the address code 17 of the address information is fed to the address buses 17, and the call signal is sent only to the input 20 of the second cycle of the local control unit of the ROM. In accordance with the reverse address code, the (- f) -and output of address part 6 is energized. At outputs 8 of the second accumulator 4, signals corresponding to the information of the i-th address bus appear. The strobe signal from the output 16 of the second clock cycle of the local control unit ROM is fed to the gate 15 of the gating of the bit amplifiers 9 of the second drive, resulting in output signals from the second drive to the OR 11 circuit. Since the information on the i buses in both drives the same, then the single inputs of the flip-flops 19 of the register of the number in the second cycle of circulation receive information confirming the information read in the first cycle.

If, as a result of a catastrophic failure of parts in one of the cycles, for example, in the first one, for any digit there is no 1 binary information, then it is entered into the number register in the additional second circulation cycle. The address in both clock cycles occurs at different addresses (forward and reverse codes of the address of the information sought), therefore in the address part 6 of the ROM there are different address shapers 5, in our example, rth and (n - 1) -th shapers. Therefore, in the address part, the drivers corresponding to the forward and reverse codes of the address are reserved in each other's work. In the address part of the prototype block

There is no reservation. Thus, the connection according to the proposed scheme allows eliminating equipment equivalent to the address part of one block without reducing the reliability of the redundant ROM.

Subject invention

A permanent storage device containing two accumulators of n numbers, bit amplifiers connected to the outputs of the accumulators, an OR OR address block, a local control block and a number register, characterized in that, in order to reduce the equipment, the t-address bus of the first accumulator connected in series with (n - 1) -th

the address width of the second accumulator and with the tm output of the address block, the gating inputs of the bit amplifiers of the first drive are connected to the output of the first cycle of local control, the gates of the bit amplifiers of the second accumulator are connected to the output of the second cycle of the local control block, outputs of bit amplifiers of the same name bits are connected to the inputs of the corresponding

“OR” circuits, “OR” circuit outputs are connected to the corresponding inputs of the number register.