SU361524A1 - PULSE DISTRIBUTOR - Google Patents

Description

one

The invention relates to a pulse technique and can be used to develop a sequence of clock pulses that synchronize the operation of all devices of a digital computer.

In known pulse distributors, failures or failures are detected by means of signal circuit solutions or by the in-circuit noise-resistant coding of distributor states.

The purpose of the invention is to increase reliability - achieved by the fact that in the proposed distributor and pulses, there are two identical shift registers and an error signal shaping device, the outputs of each trigger of one register and the outputs of the corresponding "And other register" circuits generating an error signal whose outputs are connected to the inputs of OR circuits generating an error signal.

FIG. 1 shows a block diagram of a pulse distributor; in fig. 2 - functional scheme of the shift register; in fig. 3 is a functional diagram of an error signal generation device.

The pulse distributor (Fig. 1) consists of two identical shift registers 1 ti 2 on n channels each and an error signal generating device 3.

The shift register (Fig. 2) consists of n And circuits for generating the output. Pulses - Triggers and Inverter

i

the strokes of the AND circuits are connected to the inputs of the flip-flops, and the outputs of the flip-flops are connected to the inputs of the circuits And so that a shift register is formed that operates in the Gray code. Exit 4

pulse generator (not shown in the drawing) is connected to the inputs of half of the circuits "And and to the input of the inverter" NOT 5. The output of the inverter "is NOT connected to the inputs of the other half of the circuits" I. The outputs of the circuits And the shift registers are connected to an error signal forming device 5 and to external devices that are a pulse distributor load. Trigger outputs are also connected to a signal conditioning device.

mistakes 3.

The device for generating error signals (Fig. 3) consists of 4 circuits "And 5, 7 and circuits 8-10. The inputs of the circuits "And 6 connected to the outputs of the triggers of the shift register I and the outputs of the circuits" And Sltvigovogo register 2.

The inputs of the circuits "And 7 connected to the outputs of the triggers of the shift register 2 and the outputs of the schemes" And the shift register /. The outputs of the circuit "And 6 connected to the inputs of the circuit" OR

S, the outputs of the circuit "And 7 - with the inputs of the circuit

"OR and the outputs of the circuits" OR 8 and 9 are connected to the inputs of the circuit "OR 10.

The pulse distributor operates as follows.

The input of each shift register (Fig. 2) receives a sequence of rectangular pulses from the output 4 of the pulse generator. The duration of imgaulys, and the pays between them are equal to each other. Thus, the sequence of pulses at the output of the inverter “NOT 5 in each shift register is phase shifted by 180 ° relative to the sequence of pulses from output 4. Both shift registers operate synchronously, the cycle of their operation is equal to clock cycles.

In the schemes "And 6 of the error signal generation device (Fig. 3), the state of the shift register triggers / output I1M1P ulvs are checked; The presence of a single signal at the output of any of the schemes “And 6, 7 means a failure or failure in one of the shift registers. If both shift registers operate synchronously and there are no failures and failures in either shift register, then at the outputs of the And 5 and 7 circuits of the error signal generation device there are no single signals, therefore, there is no error signal either. In the event of a failure or failure, for example, in the shift register 1, leading to the disappearance of the output pulse, the trigger controlled by this pulse does not change its state. But the output pulse of the shift register 2 at the output of the corresponding circuit "AND the error signal generating device appears a single signal, and consequently, an error signal. If a failure or failure of the shift register / wils occurs due to the appearance of a false output pulse of this register, then taking into account the personality cycle of the distributor, two cases are possible: the output pulse of this register should be one tick earlier; The output pulse of this register is wiles later by k clock ticks, where k can take values from 1 to n-, 1.

In the first case, the trigger, controlled by the pulse of the register /, earlier changes its

condition. But the output pulse of the shift register 2 at the output of the corresponding circuit "AND the signal shaping device of the error will appear a single signal, and consequently, an error signal.

In the second case, a false pulse of the shift register /, provided that the triggers controlled by the output pulses of the shift register 2 are working correctly, will cause a single signal at the outputs of the corresponding AND AND error signal generation devices. Thus, any error in the development of any output pulse will be unloaded for a time not exceeding the duration of one clock cycle.

Subject invention

A pulse distributor containing two identical shift registers consisting of triggers and AND circuits, as well as an error signal generation device consisting of AND and OR circuits, characterized in that

in order to increase reliability, the outputs of each trigger of one register and the outputs of the corresponding circuits. And the other register is connected to the inputs of the circuits AND the error signal generation device whose outputs

associated with the inputs of the OR circuit generating the error signal.

Signal

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Signal O & ki

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