SU1755279A1 - Generator of multivariable random processes - Google Patents

Abstract

The invention relates to computing and can be used to simulate random variables, processes, and fields. The purpose of the invention is to enhance the functionality by creating a correlation dependence between realizations of a multidimensional random process. The generator contains a memory register, counters, memory devices, keys, a decoder, an accumulator, a random number sensor, comparison blocks, a block of OR elements, OR elements, delay elements, and a control block. 3 il.

Description

The invention relates to the simulation of random variables and processes on computer jaax and can be used as a set-top box or an internal unit of an electronic computer.

The purpose of the invention is the extension of functionality due to the formation of an exponential-cosine correlation dependence between realizations of a multidimensional random process or sex.

The essence of the proposed device is to organize a rearrangement of the implementation of a multidimensional random process or random field with the required law of probability distribution according to the rule of choice from some initial bounded set of realization with the sum of components closest to

module to the sum of the components of the last progressed implementation. Summation of the components of implementations makes it possible to simply compare them for the subsequent selection of one implementation from their initial set. Introducing the memory register and the comparison scheme. Ensures that the control parameter of the generating process is specified — the amount of the limited set of initial implementations.

Fig, 1 shows the generator of multidimensional random fields; in fig. 2 and 3 - storage devices.

The generator contains (Fig. 1) counter 1, memory 2, decoder 3, memory 4, accumulator adder 5, key 6 comparison unit 7, key 8, counters 9, 10, keys 11-12, block of elements OR 13, element Delay 14, random number sensor 15, backslider

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16, an OR element 17, a comparison unit 18, a memory register 19, a delay element 20, a control block 21, a delay element 20, a control block 21, an OR element 22.

The memory device 2 (Fig. 2) contains a counter 23, a clock pulse generator 24, a trigger 25, a delay element 26, a decoder 27, an adder 28, a memory register 29, a comparison block 30, a trigger 31, a decoder 32, keys 33, 34, memory block 35, block 36 OR elements.

Storage Device | 4 (FIG. 3) contains a counter 37, a clock pulse generator 38, a trigger 39, a delay element 40, an element or 41, a comparison block 42, a memory register 43, a trigger 44. keys 45, 46, a memory block 47.

The information output of the counter 1 (Fig. 1) is connected to the address input of the storage device 2 and the decoder 3, the output connected to the first address input of the storage device 4. The output of the storage device 2 is connected to the information input of the adder 5 and to the information input of the storage device 4. The output of the storage device 4 through the information input of the key 6 is connected to the output bus of the entire generator.

The output of the adder 5 is connected to the first input of the comparison unit 7 and with the information input of the key 8. The output of the control unit 7 is connected to the control input of the key 6, to the control input of the key 8 and to the second (read) address input of the memory device 4.

The memory device 2, when a signal arrives at the address input, transmits the contents of K cells (where K is the number of components of the process implementation or field) to the output of the memory block. In this case, the address of the first of the K transmitted numbers is determined depending on the value of the signal at the address input.

The decoder 3 converts a multi-digit number (address) at its input into a single pulse at the output. The storage device 4 is intended for temporary storage of components of the implementation of a multidimensional random process or a random field, the sum of which calculates adder 5 and transfers these components through the key b to the generator output bus. The signal at the first (recording) address input of the device 4 provides for recording information in this block, and the signal at the second (reading) address input ensures the sequential output to the output of the memory device 4 implementation components stored in this block. Key 6 allows the transfer of information to the output bus of the generator from the storage device 4 only when determining the closest by the sum of components

from the entire set of implementations recorded in memory 2, to the last progressed implementation, the Output of the key 8 is connected to the installation inputs of counters 9 and 10. The counter 9 operates in the mode of increasing content with the arrival of the control input of the control pulse, and the estimator 10 reduction mode. The outputs of the counters 9 and 10 are connected respectively to the information inputs of the keys 11 and 12, the outputs of which are connected through the block of the OR 13 elements to the second input of the comparison block 7. The output of the comparator unit 7, in addition to the keys 6 and 8 and the storage device 4, is connected via a delay element 14 to the control input of the sensor of random uncorrelated numbers 15, the output of which is connected to the information input of the storage device 2. Sensor

5 random uncorrelated numbers 15 with the arrival of a signal at the control input generates the implementation of a multidimensional random process or random field with the required probability, which is recorded in memory 2 in the cells with addresses determined by the signals at the address input.

In addition, the output of the delay element

5 14 through the delay element 16 and the OR element 17 is connected to the zero input of the counter 1. The information output of the counter 1 is also connected to the first input of the comparison unit 18, the second input of which is connected to the output of the memory register 19, and the output of the comparison 18 through the second input of the element OR 17 is connected ((to the zero input of the counter 1 set to zero. The zero input of the adder 5 and the counting

5, the input of the counter 1 through the third delay element 20, the control inputs of the keys 11 and 12, and the counting inputs of the counters 9 and 10 are connected respectively to the output of the control unit 21. The output of block 18 is comparison and

0, the overflow output of counter 1 is connected via the OR element 22 to the input bus of the control unit 21, and the output of the comparison unit 7 is also connected to the input bus of the control unit 21.

5 Memory devices 2.4 and adder 5, when performing actions, operate with multidimensional (K - dimensional, K - 1, 2, ...) implementations of a random process, that is, process (read, write, summarize) groups K of multi-digit numbers

The storage device 2 (FIG. 2) performs two operations — writing K numbers and reading K numbers. The address for writing (or reading) the first of the numbers of the processed vector is set at the address input of the memory 2,

The counting input of the counter 23 is connected to the output of the clock generator of the memory block 24. The control input of the clock generator 24 is connected to the forward (single) output of the trigger 25, and the single input of the trigger 25 is connected through the delay element 26 to the output of the first decoder 27. The decoder 27 is connected by its input to the address input of memory 2 and is designed to convert a multi-digit number (address) into a single pulse.

The address input of the memory device 2 is also connected to the installation input of the address counter 22 and to the first input of the adder 28, the second input of which is connected to the memory register 29, which stores the dimension of the generated multidimensional random process or random field. The output of the combinational adder 28, designed to determine the storage address of the last K-th number, is connected to the first input of the comparison unit 30, the second input of which is connected to the output of the address counter 23. The output of the comparison unit 30 is connected to the inverse (zero) input of the trigger 25 and the direct (single) input of the trigger 31. The inverse (zero) input of the trigger 31 through the second decoder 32 is connected to the input information bus of the storage device 2. The decoder 31 converts the multi-digit by its entrance to a single impulse.

The zero output of the trigger 31 through the key 33, and the single input of the trigger 31 through the key 34 are connected respectively to the control recording and reading inputs of the memory unit 35. The enabling inputs of the keys 33 and 34 are connected to the output of the clock pulse generator 24, the signal on the control, recording input provides only the recording of information in block 35, and the signal on the control, reading input only reads information on block 35. The address of the entry ( or reading) is fed to the address input of the unit 35 from the output of the address counter 23. The information input of the unit 35 is connected to the information input of the device. The same bus through the first input of the block OR 36 is connected to the output of the storage device 2. In this case, the second input of the block of elements OR 36 is connected to the output of the block 35.

The storage device 4 (FIG. 3), as well as the storage device 2, performs two operations — writing and reading K numbers. The difference between the device 4 and

device 2 consists in the fact that in device 2 it is necessary to store a number of realizations of the random K-dimensional process or field, and in device 4 it is necessary to store only one implementation. Therefore, the principles of operation of devices 2 and 4 are the same and the only difference is in the method of specifying the addresses and the end of the write (reading) K of random numbers that form the realization of the generated random process or field,

5 In the memory 4, the counting input of the address counter 37 is connected to the output of the clock generator 38. The control input of the clock generator 38 is connected to the single (direct 0) com output of the trigger 39, the single (direct) input of which is connected via output element OR 41.

The OR 41 element is connected by inputs to the first and second control buses of device 4, and the output of the OR element 41, besides the delay element 40), is connected to the address counter 37 installed at the starting address.

The address output of the address counter 37 is connected to the first input of the comparator unit 42, the second input of which is connected to the memory register 43, which stores the storage address of the last number in the device 4. The output of the comparator unit 42, the signal that appears for 5 s in case of coincidence of addresses at the inputs of this block 42, the comparison is connected to the zero (inverse) input of the trigger 39.

The first control input bus of the storage device 4 connected

0 to the output of the device decoder 3, connected to the zero (inverse) input of the trigger 44. The second control input bus of the device 4 connected to the output of the device comparison unit 7 is connected to the single (direct) input of the trigger 44. The zero (inverse) output of the trigger 44 and the direct (single) output of the trigger 44 are connected to the first inputs of the keys 45 and 46, respectively. The second inputs of the keys 45

0 and 46 are connected to the output of the clock pulse generator 38. The outputs of the keys 45 and 46 are connected to a control, respectively, recording and reading input of block 47. The address input of block 47

5 is connected to the output of the counter address 37.

The information input of the storage device 4 through the information input bus device 4 is connected to the output of the device 2 of the entire random process generator and fields, and the output of the block 47

through the information output bus device 4 is connected to the information input of the key b (Fig. 1).

The generator of multidimensional random processes works as follows.

In the initial position, the counter 1 is set to the initial (zero) state. The memory register 19 contains an integer that defines the volume of a limited set of initial realizations of a random multidimensional process or gender, which ensures the selection of the process (floor) nearest to the last progressed implementation. The contents of memory register 19 is a generator parameter that controls the correlation value. Memory 2 contains independent implementations of a random process (pop). Counters 9 and 10 contain the sum of the components of the implementation of a multidimensional process (gender). The process (floor) implementations have the required probability distribution, specified by a sensor of random uncorrelated numbers 15. At the output of the black 7 comparison, there is no signal, therefore key 8 is locked and the inputs of counters 9 and 10 are not supplied with the sum of the implementation components from the output of the adder 5. For the same reason, the key 6 is locked and there is no signal at the reading input of the memory 4, which results in the absence of numbers at the output of the device. At the output of the comparator unit 11, there is also no signal.

The pulses from the clock generator of the control unit 21 are transmitted to the zeroed input of the adder 5, through the delay element 20 to the counting input of the counter 1 and to the enabling input of the key 11. The counter 1 sets the next value of the device 2 address, which first , to the address input device 2; secondly, through the decoder 3, which converts the address into a signal, to the recording input of the memory 4; thirdly, the address from the counters 1 is fed to the input of the comparison unit 18. The signal at the output of comparison unit 18 appears only if the address in counter 2 has reached the maximum value determined by the contents of memory register 19. The number recorded in register 19 is intended to control the magnitude of the correlation dependence between realizations of the multidimensional random variable. process of play As it increases, the correlation value of w / oo moments increases, since correlation is introduced by selecting from the set of implementations stored in device 2 to the previously generated implementation according to the rule of minimizing the modulus of the difference between the sum of the components of the previously generated last implementation and selected from device 2 implementation.

The more different implementations are compared, the more opportunities there are for the selection of the closest-in-order implementation in comparison with the last generated implementation, and, therefore, the correlation value is significantly larger. Therefore, in register 19 any number can be written, including more than the number of realizations that device 2 can store. The signal at the output of the comparison unit 18 is similar in effect on the operation of the generator and the signal at the output of the counter overflow 1 Both of these signals are fed to the inputs of the element OR 22, the output of which is connected to the control unit 21, In accordance with the address recorded in the counter 1, the output of the device 2 is sent to the numbers that are transmitted to the input of the adder 5 and to the input of the device 4, where and

stored before the arrival of the signal at the read input. After summing up in the adder 5 implementation components, this sum goes to the information input of the key 8 and to the first information input.

block 7 comparison.

The second information input of the comparison block 7 through the key 11 and the block of elements OR 13 enters the number recorded earlier in the counter 9. At the output of the comparison block 7

by whits signal if a comparison has occurred; otherwise, the signal is not generated. Consequently, the components of the process implementation or the field recorded in the device 4 are not sent to the generator output. Due to the lack of a signal at the output of the comparison block 7, the key 8 is also locked and the sum from the output of the adder 5 is not fed to the installation inputs of counters 9 and 10. The generator will work in the same way until a comparison signal is produced at the output of the comparison unit, or the counter 1 overflows, or the comparison in the comparison unit 18.

Let counter 1 overflow (or a comparison in the comparison circuit 18), that is, a successive comparison be made to the number of process or field implementations specified by the contents of memory register 19). Counter 1 through the element OR 17 is transferred to its original position. At the output of the overflow of the counter 1 or at the exit of the comparator unit 18, the signal that enters the control unit 21 appears.

The next pulse from the control unit 21 is transmitted to the counting input of the counter 10, reducing its content by one.

Then the adder 5 is reset to the zero state and the same signal passing through the delay element 20 is fed to the counting input of the counter 1, after which the signal is transmitted to the control input of the key 12. The appearance of the new address at the output of the counter 1 causes see previously recorded operations That is, at the output of the memory device 2, the implementation components appear, which are written to the device 4 with the help of the decoder 3. The same K numbers are summed by the adder 5 and the sum is fed to the information input of the key 8 and the input of the comparison unit, If on As the comparison block 18 progresses or the output overflows from the counter 1, signals appear, then the actions on them are described and the presence of at least one of these signals means the end of the generation cycle. If these signals are not present, then to the second input of the comparison block 7 through the key 12 and the block the elements OR 13 enters the contents of the counter 10. In the case of coincidence of the numbers received at the inputs of the control unit 7, the output at its output is given by a VITS signal. Otherwise, the generator will repeat the comparison cycle by generating a new pulse from the output of control block 21,

If a comparison of all the specified contents of the memory register 19 or the device volume 2 of the sum of the components of the random process or field implementations with the contents of the counter 10 does not occur, then the output of the overflow of counter 1 or the output of the comparison unit 18 gives the trigger signal 21,

The next impulse of the control unit is transmitted to the counting input of the counter 9, increasing its content by one. Further, the operation of the generator continues according to the described scheme until a comparison is made of the number at the output of the adder 5 with the contents of one of the counters 9 or 10.

If at the output of the comparator unit 7 a comparison signal is turned on, it opens the key 76 and initiates the reading of information from the device 4 for transmitting it to the generator output. The same signal from the output of the comparator block 7 opens the key 8 and the sum from the output of the adder 5 is recorded in counters 9 and 10. This sum of the components of the implementation of the random multidimensional process or the random floor is closest to the sum of the components of the last progressed implementation of the random process or sex. And finally, this is the same signal from the output of the delay element 14 is fed to the input

The sensor of random uncorrelated numbers 15 and the input of delay element 16. The sensor of random uncorrelated numbers 15 produces an implementation of a multidimensional random process or field, which is recorded at the point of sale received at the generator output, since the address value in counter 1 has not changed since the output of delay element 16 signal

0 is transmitted through the OR element 17 to the installation input of the counter 1 and sets it to the initial state corresponding to the initial address of the device 2. This translates the generator to the initial state and

The 5 cycle of operation of the generator of multidimensional random processes and fields ends.

When the device 2, like other blocks and the generator as a whole, we will proceed from the fact that K of the numbers forming

0, the next implementation of a multi-dimensional random process or gender, is fed over the respective tires sequentially. Before writing or reading information, the trigger 23 is at zero.

5, and the trigger 31 is in the single state, which is always provided by the output signal of the comparison circuit 30.

When reading 4 numbers of the block 35, the address input bus of the device 2 is fed

0 is the address of the first number, and there is no information on the information input bus. The address is fed to the input of the combinational adder 38, where, using the contents of the memory register 39

5 (dimensionality of the generated process), the final address is calculated at which the last (K-e) number of the implementation of the multidimensional random process or random field is stored. The calculated (final) adode is fed to the input of the comparison unit 40. The starting address from the input address bus of the device 2 is recorded through the setup input to the address 23 counter. This same address, converted to a single impulse de 5 by the encoder 27, passed through the delay element 26, enters the single input of the trigger 25 and translates it into a single state. The signal at the single output of the trigger 25 starts the clock generator

0 pulses 24, the frequency of the pulses at the output of which is substantially higher than the frequency of the pulses at the output of the control unit 21.

The signal from the output of the generator of clock pulses 24 is supplied to enable

5, the inputs of the keys 33 and 34, and since the trigger 33 is in the single state, the key 33 remains closed, and the key 34 opens and the signal at its output goes to the read input of the block 35. Since the counter 23 by means of the clock pulse generator 24 will be sequentially installed in the state corresponding to the first number of the implementation of a multidimensional random process, the second number, and so on, and these addresses also go to the address input of the block 35, then the output and the output of the device 2 will be received implementation of a multidimensional stochastic process, stored in block 35, starting from the specified address.

The end of the reading is determined by the coincidence of the addresses at the inputs of the comparison unit 30 and the generation of the corresponding signal at its output. By this signal, the trigger 35 is brought to the zero state.

Information is recorded in block 35 similarly, with the difference that the appearance of information on the input bus of the storage device 2 leads, first, to transmitting it through the block of elements OR 34 to the input bus of the device 2; secondly, after the decoder 32 converts this unit to a single HN. in this information, it switches the trigger 31 to the zero state, which opens the key 33 and closes the key 34 (i.e., the signal goes to the recording input of the memory 35 and thirdly, supplying this information to the information input of block 35, Determining the address of the last record, calculating and submitting addresses to the address input of block 35, starting and stopping the clock pulse generator 24 are performed in the same way as when reading information.

In the storage device 4, before starting to write or read information, the address counter 37 is set to the state corresponding to the starting address of block 47, and the first trigger 39 to the zero state.

The write operation of K numbers in device 4 starts with the arrival of a signal at its control input from decoder 3. This signal switches trigger 44 to the zero state and from the zero output of trigger 34 a signal arrives at the control input of key 45, the signal also flows through the OR element 41 to the input of the delay element 40 and the input of the address counter 37, which is set to the starting address. The signal from the output of the delay element 40 goes to the single input of the trigger 39, from a single (direct) output of which the signal starts the clock pulse generator 38, the frequency gene Pulse pulsing is significantly higher than the pulse / pulse generation frequency of control unit 21. Output pulses

the clock pulse generator 38 is fed to the control input of the key 45, thereby providing a pulse to the recording input of the block 47, i.e. block 47,

is brought into a state that records K-numbers from the information input of the device. At the same time, the addresses at the address input of the block 47 are formed by the address counter 37. The formation of the address is maintained until it coincides with the final address stored in memory register 43, and the comparison block 42 does not reproduce the signal at its output. the signal at the output of the comparison block 42

the trigger 37 is switched to the zero state, and the clock pulse generator 33 stops the generation of pulses. The write operation of K numbers to the device 4 is completed,

The read operation of K numbers from device 4 is carried out similarly to a write operation, with the only difference that the initial signal arrives at the input of the element OR 41 through the single input of the trigger 44, having established it in the single state, enters the control input of the key 46, ensuring that Gamy signal on the reading input unit 47.

Thus block 47 is reduced to

a state that reads K numbers from it, which form the realization of the generated multidimensional random process or random field at the output of the memory device c. In this case, the order of starting the block, the formation of addresses and the stop of the generator of clock pulses 38 remain the same as when performing a write operation.

Claims (1)

Invention Formula Multidimensional random process generator, containing the first memory block, three sensors, the first comparison unit, three keys, two delay elements, the first block the OR elements, the control unit and the random number sensor, the output of which is connected to the information input of the first memory block, the output Equals the first comparison block connected to the mode reference input the control unit, to the input of the first delay element and through the second delay element to the trigger input of the random number sensor, the first and second inputs of the control unit are connected to the control inputs of the first l of the second keys, whose outputs are connected to the inputs of the first block of OR elements whose output is connected with the first input of the first comparison unit, the output of the third key is connected to the information inputs of the first and second counters, the outputs of which are connected to the information inputs of the keys of the same name, and the counting inputs are connected respectively to the third and fourth outputs of the control unit, characterized in that, in order to extend the functionality by creating a correlation dependence between realizations of the multidimensional random process, the second block is entered into it memory, two clock generators, four triggers, three decoders, three comparison blocks, two counters, five keys, three delay elements, three memory registers, the second the block of elements OR, three elements OR, the adder and accumulating adder, the output of which is connected to the second input of the first comparison unit, the output Equal to which is connected to the control inputs of the third and fourth keys, to the first input of the first element OR, and to the single input of the first trigger, etc. my and inverse outputs of which are connected to the control inputs of the fifth and sixth keys, the outputs of which are connected respectively to the recording and reading control inputs of the second memory block, the output of which is connected to the information input The fourth key, the output of which is the generator output, the output of the random number sensor is connected to the input of the first decoder and to the first input of the second block of OR elements, the second input of which is connected to the output of the first memory block, and the output is connected to the information input of the second block and the information input of the accumulating adder, the output is connected to the second input of the first comparison unit and to the information input of the third key, the clock input of which is connected to the fifth output of the control unit connected through the third the delay element with the counting input of the third counter, the output of which is connected to the inputs of the second and third decoders, to the information input of the fourth counter and to the first input of the adder, the second input of which is connected to the output of the first memory register, and the output connected to the first input of the second block comparison, the second input of which is connected to the output of the fourth counter connected to the address input of the first memory block, the output is equal to the second comparison block connected to the S-input of the second trigger and to the R input of the third trigger, the direct output of which is connected to the start input of the first clock pulse generator; the output of which is connected to the counting input of the fourth counter and to the information inputs of the seventh and eighth keys, the outputs of which are connected respectively to the write and read control inputs of the first memory block, the output of the first the decoder is connected to the R-input of the second trigger, the inverse and direct outputs of which are connected respectively to the control inputs of the seventh and eighth keys, the output of the third decoder through the fourth delay element is connected to the S input of the third trigger, the output of the second decoder is connected to the zero input of the first trigger and to the second input of the first OR element, the output of which is connected to the installation input of the fifth counter and through the fifth delay element - with the S input of the fourth trigger, the direct output of which is connected to the start input of the second clock generator, the output of which connected to the counting input of the fifth counter and with the information inputs of the fifth and sixth keys; the output of the fifth counter is connected to the information input of the second memory block and to the first input of the third comparison unit, the second input of which is connected to the output of the second memory register, and the output Equal to the R input of the fourth trigger, the first and second inputs of the fourth comparison block are connected respectively to the outputs of the third memory register and the third counter, and the output Equal to the first the inputs of the second and third elements OR, the second input of which is connected to the output of the second element delays, and the output is with the installation input of the third counter, the overflow output of which is connected to the second input of the second OR element, the output of which is connected to the start input of the control unit. 15  l 15 - & t dddlmsh 2 five 17 J 22 21 22 -Ј 1 31 g: 33 J4 35 3L 4 8 13 eleven 12 / 7 28 26 YES I g 24 ЈJ #W f Editor I. Casard Tehred M. Morgenthal Order 2894 Circulation: Subscription VNIIPI State Committee on Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nzb, 4/5 FIG. 3 Proofreader L.Lukam