SU1746522A1 - Device for control of delay of pulses - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices of measuring technology, in information processing devices, in which a delay for a given time of pulses of a given duration is effected, as well as for measuring the duration in pulsed radars and reflection simulators. The purpose of the invention is to extend the functionality by providing control of the delayed pulse duration regardless of the duration of the delayed pulse. The device for controlled delay of pulses contains a clock pulse generator, two reversible counters, a trigger, an input bus of delayed pulses, an output bus, a frequency divider, a switch, an adder, a third reversible counter, an initial setup input, a static delay information input, an information input of a dynamic delay, reversal input, delayed pulse duration input, information output of the current delay value. 4 il. you

Description

The invention relates to a pulse technique and can be used in devices of measuring technology, in information processing devices, in which a delay for a given time of pulses of a given duration is effected, as well as for measuring the duration in pulsed radars and reflection simulators,

The purpose of the invention is to extend the functionality by providing control of the delayed pulse duration independently of the delayed pulse duration.

FIG. 1 shows a functional diagram of the proposed device for controlled pulse delay; in fig. 3 is a diagram of operation of the clock pulse generator; in fig. 4 is a diagram of the operation of the device in the static delay mode; on

FIG. 2 is a schematic diagram of a clock pulse generator.

The device (Fig. 1) consists of a clock pulse generator 1 for issuing highly stable clock pulses at predetermined time intervals, a frequency divider 2 for dividing the frequency of delayed pulses with a dividing factor depending on a given rate of change of the delay, switch 3 designed to change the sign of the rate of change of the dynamic component of the delay, the adder 4. designed to add the static and dynamic component of the delay, the first reversible counter 5 which counts the dynamic component of delay, a second down counter 6, intended for converting an information delay value in real delay time, the third down counter 7, providing a predetermined delayed pulse duration, and a trigger 8 for forming a delayed pulse. The information output 9 of the current delay value is connected to the output of the adder A and the information input of the second counter 6, the transfer output of which is connected to the single input of the trigger 8 and the third input of the clock pulse generator 1, the first input of which is connected to the input bus 10 of the delayed pulses and the second input of the divider 2 frequency, the first input of which is connected to the information input 11 of the dynamic delay of the device. The information input 12 of the static delay of the device is connected to the first summing input of the adder 4, the second summing input of which is connected to the information output of the first counter 5, the summing and subtracting inputs of which are connected respectively to the first and second outputs of the switch 3, the first and second inputs of which are connected respectively to the output divider 2 frequency and input 13 reverse device. The input 14 of the initial installation of the device is connected to the zero input of the first counter 5. The zero input of the second counter 6 and the zero input of the third counter 7, the transfer output of which is connected to the second input of the clock pulse generator 1, and the single trigger input 8, the output of which is the output bus 15 of the device. The input 16 of the duration of the delayed pulse of the device is connected to the information input of the third counter 7, the subtracting input of which is connected to the second output of the clock generator 1, the first output of which is connected to the subtracting input of the second counter 6.

The clock pulse generator 1 (Fig. 2) consists of the first and second pulse generators 17 and 18, stabilized by a common quartz resonator 19, and two triggers 20 and 21, gating the operation of the pulse generators 17 and 18 at predetermined time intervals. The output of the first trigger 20 is connected to the zero input of the first generator 17 of pulses, the synchronous inputs of which are connected to the plates of a quartz resonator 19 and the corresponding synchronous inputs of the second generator. 18 pulses, the zero input of which is connected to the output of the second trigger 21. A single input of which is connected to the zero output of the first trigger 20 and is the third input of the clock generator 1 connected to the output of the unit 6 of the device. The first input of the generator 1 clock pulses connected to the input

bus 10 delayed pulses of the device, is the single input of the first trigger 20, and the second, connected to the output of the device block 7, is the zeroing input of the second trigger 21. The outputs of the clock generator 1, respectively, are first output connected to the input of the device block 6, The first pulse generator 17, the second connected to the input of the unit 7 device, is the output of the second pulse generator 18.

Clock generator 1 can be made on the basis of an IC of the 530 GP series and 533 TP2, frequency stabilization is carried out using a quartz resonator WP-05ET-10,000 kHz, Counters 5-7 can be performed on the IC 533 IE7, trigger 8 - IC 533 TP2. Frequency divider 2 can be an IC 633 IE7 chain. Switch 3 is made on the IC 533 LAZ.

5 The device operates as follows.

To bring the device back to its original state after applying a supply voltage to it, it is necessary to connect it to

0 input bus 10 delayed pulses delayed pulses, information input 12 of the static delay and input 13 reverse reverse, and input 16 of the duration of the delayed pulse to submit a digital code corresponding to the specified pulse duration. The state of the information input 11 of the dynamic delay makes no difference.

The device comes to its initial state after the input to the 14 of the initial setup of the NU signal in the form of a low-level pulse of arbitrary duration. In this case, the first counter 5 is zeroed and held in this state due to the lack of signals on the counting inputs from the output of the switch 3, since the latter is closed on both outputs by applying the zero reverse code to the reverse input 13. On the summing inputs of the adder 4 with information

0 input 12 of the static delay and the information output of the first counter 5 are given zero codes - the output of the adder 4 is zero. The operation of the clock 1 generator in the initial state can be described by the diagram shown in FIG. 3, where the following symbols are accepted: a -, the signal diagram at the first input of the 1 clock generator; b - a diagram of signals at the second input of the generator 1 clock pulses; in-chart signals on

the third input of the clock 1 pulse generator; g - the natural frequency of generation of the generator 1 clock pulses; d - diagram of the signals at the first output of the generator 1 clock pulses; e - diagram of signals at the second output of the generator 1 clock pulses.

In the initial state, a delayed pulse arriving at the first input of the generator 1 clock pulses; sets the first trigger 20 to a high state and thereby enables the generation of a clock frequency from the output 17 of the pulse generator, which is the first output of the generator of 1 clock pulses. But since the adder 4 outputs a zero code to the input of counter 6, an attempt to count to zero the contents of counter b leads to the appearance of a transfer pulse from its output that hits the third input of the generator 1 clock pulses and zeroing trigger 20, which prohibits further generation frequency from the first generator output 1 clock pulses. Thus, the result of the operation of the clock frequency generator in the initial state on the first output is a single clock frequency pulse, the front of which coincides with the decay of the delayed pulses. The third counter 7 operates in a cyclic mode. Subtracting up to zero the value supplied to its information input from the input 16 of the device’s delayed pulse duration. The origin of the counter corresponds to the transfer pulse from the output of the second counter 6, which sets the trigger 21 of the clock generator to a high level, thereby allowing the generation of the frequency from the second generator output 1 of the clock frequency. At the end of the recalculation, the transfer pulse from the output of the third counter 7 closes the generator of 1 clock pulses at the second input, stopping the generation until the next delayed pulse arrives. Thus, the trigger of the device 8 receives two transfer pulses: a single input from the output of the second counter 6 and an embedding input from the output of the counter 7. The trigger 8 forms a delayed pulse whose front coincides with the transfer pulse from the second counter 6 , and the decline - with the momentum transfer from the third counter 7.

The result of the operation of the device in the initial state is a pulse of a given duration formed on the output bus 15, the front of which coincides with the decline of the delayed pulses. Information output 9 current

the delay value contains a zero value.

The device has two modes of operation - the static delay mode (the mode is similar to the operation of the known device) and the dynamic delay mode.

In the static delay mode, the delay of the output pulses relative to the input pulse series is equal to the specified value, constant and independent of the device operation time. To operate the device in the mode of information input 12 of a static delay, it is necessary to submit a digital code corresponding to the required delay time, the value of which is calculated by the formula

t ass

tnep

where t-ass is the required delay time;

tnep - the value of the period of the clock frequency.

This code falls on the first summing input of the adder 4.. Since the second input of the adder 4 is supplied with a zero code from the output of the first counter 5, the output value of the adder 4 will be equal to the value of its first summing input. The information from the output of the adder is fed to the information output 9 of the current delay value and to the input of the second counter 6. The second counter 6 is clocked by the clock pulse generator 1, which opens on the first output with the arrival of the delayed pulse. The time taken by the second counter 6 to subtract to zero the value of the code received at its information input will be the desired delay time. The transfer pulse of the second counter 6 closes the generator 1 clock pulses on the first output, overwrites the code 6 from the output of the adder 4 to the second counter and sets the trigger 8 to the high level position, forming the front of the delayed pulse.

The decay of the delayed pulse is formed in a manner similar to the initial state,

With the arrival of a new delayed pulse, the operation of the device is repeated.

The device operation diagram in the static delay mode is shown in FIG. 4, where the following notation is accepted: a is a diagram of signals on the input bus 10 delayed pulses; b is the natural frequency of generation of the generator 1 clock pulses; in - transfer pulses from the output of the second reversible counter 6; g - transfer pulses from the output of the third reversible counter 7; d - signal diagram

at the first output of the generator 1 clock pulses; e is a diagram of signals at the second generator output t clock pulses; W - diagram of signals on the output bus 15 of the device:

To change the delay time when the device is operating in the static delay mode, it is necessary to send a signal to the input device 14 of the initial installation of the device and change the code applied to the information input 12 of the static delay, the duration of the signal from the НУ should exceed the installation time of the new code to eliminate possible failures .

In the dynamic delay mode, the delay of the output pulses relative to the input pulse series during the device operation time varies with a constant speed. This is achieved as follows. The value of the digital code supplied to the information input 12 of the static delay, using the adder 4 is added to the growing or decreasing with a constant speed value of the dynamic delay component from the output of the first counter 5. The speed of changes in the value of the first counter 5 depends on the period of clocking it pulses from the output of the splitter 2 frequency through the switch 3, which, depending on the information on the input 13 of the reverse of the device, connects the clock pulses to the summing or subtracting input of the first 5. The timing counter of the first counter 5 pulses obtained by dividing the frequency of delayed pulses supplied to the input bus 10 to a second input of the frequency divider 2. The frequency division factor 2, i.e. the code to be supplied to the information input 11 of the dynamic delay is calculated by the formula

vtnep

Kdvl Tai V

where tnep is the period of the clock frequency, μs;

Tay - the period of following delayed pulses, µs;

V is the rate of change of the delay, µs / s.

Thus, for the device to operate in the dynamic delay mode, it is necessary to input a code to the dynamic delay input 11. corresponding to the frequency division factor calculated by the above formula for a given delay increment rate, and the input corresponding to the desired sign of the delay increment to the input 13 of the reverse. For the rest

the operation of the device does not differ from the operation in the static delay mode. To change the delay increment rate in absolute value, it is necessary to change the code at the information input 11 of the dynamic delay, and by sign, change the code at the input 13 of the reverse. Changing the speed of the increment of the delay can be made at any time device operation time.

Claims (1)

Apparatus of the Invention A device for controlling a delayed pulse, comprising a clock generator pulses, two reversible counters, trigger, delayed pulse input bus, output bus, characterized in that, in order to expand the functionality of the device by providing control of the delayed pulse duration regardless of the delayed pulse duration, a frequency divider, switch, adder, and a third reversible counter, input initial setup, static delay information input, dynamic delay information input, reverse input, delayed pulse duration input and information output of the current delay value connected to the output of the adder and information input of the second reversible counter, the transfer output of which is connected to the single trigger input, second power input reversible counter and the third input of the clock generator, the first input of which is connected to the input bus of the delayed pulses vt by the second input of the frequency dividers, the first input of which connected to the information input of the dynamic delay of the device, the information input of the static delay of the device is connected to the first summing input of the adder, the second summing input of which is connected to the information output of the first reversible counter, the summing and subtracting inputs of which are connected respectively to the first and second outputs of the switch, the first and the second inputs of which are connected respectively to the output of the frequency divider and the input of the reverse of the device, the input of the initial installation of the device is connected to tilting entrance the first reversible counter, the zero input of the second reversible counter and the zero input of the third reversing counter, the transfer output of which is connected to the second clock generator input, the third reversible counter input input and the single trigger input, the output of which is connected to the output bus of the device, delayed pulse input device is connected to the information input of the third reversible counter, the subtracting input of which is connected to the second output of the clock pulse generator s, the first output is connected to a subtraction input of the second down counter. Yr one "} h : ZJWWIJL: P L n n LI IT 1PLLLG Wit