SU1735868A1 - The device to perform operations over matrix - Google Patents

Abstract

The invention relates to automation and computing and can be used in specialized matrix computers. The purpose of the invention is to expand the functionality by calculating expressions of the form X CA B + D. The goal is achieved by introducing II computational modules (M is the number of columns of the C matrix) with connections in the device. The device operates in accordance with the Fadtsevva algorithm with partial selection of the leading element. 4 il.

Description

The invention relates to automation and computing and can be used in the construction of specialized, including systolic, devices designed to perform operations on the matrices.

A device for operations on matrices is known, containing appropriately connected n operational blocks (where n is the order of matrixes being processed), (n − 1) latch elements and a pulse distributor connected to control inputs. all operating units. The device allows the LU decomposition of either inverting the original matrix or solving a system of n linear algebraic equations using the Jordan-Gauss method with a period of 2 times.

The disadvantages of this device are high hardware costs, as well as comparatively low computational accuracy due to the implementation of all algorithms without the choice of the leading element.

The closest to the invention in technical essence is a device for multiplying a matrix by a vector, containing n serially connected computing modules and a control unit.

A disadvantage of the known device is its relatively small functionality.

The aim of the invention is to expand the functionality of the device by implementing the Faddeev algorithm with a partial choice of the leading element, which allows to calculate an expression of the form X e B +

(/

WITH

sj

from cn

00 0 00

{

 B, where AJjnunj,,, and are matrices (in the particular case, with H 1, p 1, matrices C, B, and matrix D can be vectors of dimension n and scalar, respectively). Figure 1 shows a block diagram of a device for matrix operations; 2 is a structural diagram of the synchronization unit in FIG. 3 and 4 is a structural diagram of a computing module of the first and second types, respectively.

The device for matrix operations contains computational modules 1.1-1.1 of the first type and 2.1-2.2M of the second type and synchronization unit 3, the device start input is connected to the same input of block 3, the output of which is connected to the synchronous computation module 1.1, synchronization output, the output of the row permutation feature and the information output of the computing module 1. К (К -) are connected respectively to the synchronous input, the input, the sign of the line permutation and the first information input of the computing module 1.SK-Н), the second information The input of the computational module 1.P (P 1, p) is the Pm information input of the device, the synchronous input, the sign of the row permutation and the first information input of the computation module 2. g (r 1, M) are connected to the same outputs of the computation module 2 . (r-1), the second information input and output of the computation module 2.g are, respectively, (n + r) -m information input and the rth output of the device.

I

Computing Module 1.P contains

4.P multiplication-division unit, the first input of which is connected to the output of the first register 5, P, the input of which is connected to the output of the first switch 6.P and to the input of the second register 7.P, the output of which is connected to the first inputs of the first 6.P and second 8.P switches and a 9.P comparison circuit, the second input of which is connected to the second inputs of switches B.P. and 8.P and to the output of the third switch 10.P, the first input of which is the second information input of the computation module, the first information input which is associated with the first inputs of the fourth 11.P and p addition 12.P switches, the second input Last pod15

20

25

It is connected to the output of the block 4.P and to the first input of the adder 13.P, the second input of which is connected with the second input of the switch 11.P and the first output of the first block 14.P of the delay elements, the second output of which is connected with the input of the first D-trigger 15.P, the output of which is connected to the control input

"D register 5.P to the decrementing input of the first counter 23.P and to the zeroing input of the synchronous RS flip-flop 16.P, the output of which is connected to the first inputs of the first element OR 17.P and element AND 18.P, whose second input is The output of the 9.P comparison circuit, and its output are connected to the second input of the sixth switch 19.P, the first input of which is the input of the sign of the permutation of rows of the computing module, the first and second inputs of which are connected to the inputs of the second 20.P and the third 21, respectively. P D-flip-flops, the output of the latter is connected to the lane the second input of the PLI 22, to the second input of the block 14.P, the input of the trigger setup 16.P, the decrementing input of the second counter 24.P and is the second bit of the sync output of the computing module, the first bit of which is connected to the trigger output 20.P, to the control input of the switch 10.P and to the mode selection input (parallel entry of information or

35) counters 23.P and 24.P, the output of counter 23.P is connected to the control input of the unit 14.P, the first input of which is connected to the output of the switch 8.P, the control inputs of the switch

40 6.P and 8.P are combined and connected to the output of the element OR 22, the second input of which is connected to the input of the fourth D-flip-flop 25.P and the output of the switch 19.P whose control input

45 is connected to the negative transfer output of the counter 24.P and to the second input of the OR 17.P element, the output of which is connected to the mode select input of the 4.P block and to the control inputs of the switches 11.P and 12.P, the output of the switch 12. P is connected to the input of register 26.P, the output of which is the first information output of the computing module, the output of the sign of the interruption of the rows of which is connected to the output of the D flip-flop 25.P, the output of the switch 11.P is connected to the second input of the 4.P block, output adder 13.R - to the input of block 27.R, the output of which is connected with

thirty

the second input of the switch 10.P, the control input of the unit 27.P. is connected with the input P of the device.

Computing module 2.K contains a multiplier 28.K, the first (K 1.11) whose input is associated with the output of the first register 29.K, the input of which is connected to the output of the first switch 30.K and to the input of the second register 31.K, output which is connected to the first inputs of the first 30.K and second 32.K switches, the second inputs of which are connected to the output of the third switch 33.K, the first input of which is the second information input of the module, the first and second bits of the synchronous input and modules are respectively in first 34.K, second 35.K and third 35.K D-flip-flops, the outputs of which are respectively the first and second bits of the output

The lution of the input of block 40.K is connected with the input of the P device.

The device for operations on matrices is designed to calculate using the Faddeev expression of the form X B + D, where in general L is ajj, B is {b; K, C is seD, and D are matrices represented as a combined matrix, and The algorithm reduces to the fact that, after zeroing in the combined matrix of the lower left quadrant (i.e., the elements of the matrix C), in the right bottom, in a square (in place of the matrix D), get the desired result Xfpxlfj:

20

In fact, this expression allows one to solve several additional problems, namely: solving a system of linear algebraic equations with no

synchronization and the output of the sign by many (or one, depending on

restoring the lines of the computational module, the second and first information outputs of which are connected respectively to the outputs of the third 37.K and fourth 38.K registers, the last input is the first information input of the module and connected to the second input of the multiplier 28.K, the output of which is connected with the first input of the adder 39.K, the output of which is connected to the inputs of the register 37.K and the first block 40.K of the delay elements, the output of which is the second input of the switch 33.K, whose control input is connected to the output of the D-flip-flop 34. and to the entrance choice mode (parallel entry of information or account) of the counter 41.K, the output of which is the control input of the second block 42.K of the delay elements, the first output and input of which are connected respectively to the second input of the adder 39.K and to the output of the switch 32.К the control inputs of the switches 30.K and 32.K are combined and connected to the output of the element OR 43.K, the first and second 50 inputs of which are connected respectively to the input of the trigger 36.K and to the output of the trigger 35.K, the control input of the register 29. To is connected to the decrement from dimension C) with the right parts :

t, D 0; appeal

X at C

matrices X A with, multiplication of matrices (or matrices) by

-n vector depending on the dimension of B: X С-В with A - I, D 0; multiplication with addition of matrices X - С1В + D with А I; the problem of adaptive filtering, which uses the expression X + D for B I, where I is one 35 per matrix.

The zeroing of the lower left quadrant of the combined matrix can be done by applying the Gauss elimination to it, before bringing the matrix A

40 to the upper triangular form. Then automatically in place of -C, a zero matrix is obtained. At the same time, in order to ensure numerical stability of computations, the mat-i transform

45A is performed according to the Gauss elimination algorithm with a partial selection of the leading element in the column. What is more, at the ith step (i 1, p-1U of the Gauss algorithm, the elimination of the elements a1. (J i + 1, p) belonging to the original matrix А А (when) the partially transformed matrix A1 (with i 1) , precedes their sequential comparison with the element input of the counter 41. K and to the output S5 then ab if the next element of the fourth D-flip-flop 44.K, the input la} il | a ;; i. is ceased to be the second output the block of the j-th and i-th lines, i.e. the i-line becomes the j-th line and vice versa. In the opposite case, the permutations of the lines do not

ka 42.K, the second input of which is connected to the output of the D-flip-flop 35.K, controlled

0

on dimension B) by the right parts:

t, D 0; appeal

X at C

matrices X A with, multiplication of matrices (or matrices) by

n is a vector depending on the dimension of B: X С-В with A - I, D 0; multiplication with addition of matrices X - С1В + D with А I; the problem of adaptive filtering, which uses the expression X + D for В I, where I is unity per matrix.

The zeroing of the lower left quadrant of the combined matrix can be done by applying the Gauss elimination to it, before bringing the matrix A

0 to the upper triangular view. Then automatically in place of -C, a zero matrix is obtained. At the same time, in order to ensure numerical stability of computations, the mat-i transform

A and A are executed using a Gaussian elimination algorithm with a partial selection of the leading element in a column. What is more, at the ith step (i 1, p-1U of the Gauss algorithm, the elimination of the elements a1. (J i + 1, p) belonging to the original matrix А А (when) the partially transformed matrix A1 (with i 1) , they are preceded by a sequential comparison with the element5 then ab if the next element la} il | a ;; i. is carried out to interchange the jth and i-th lines, i.e. i-frameto ab if the next element la} il | a ;; i. the rearrangement of the j-th and i-th rows is performed, i.e. the i-row becomes the j-th row and vice versa. In the opposite case, the permutations of the rows are not

one

going on. Only after all (at this step) operations of comparison and permutations (i.e. the process of selecting the leading element) are completed, do you begin

and

the process of eliminating the elements aj of converting rows from (1 + 1) th to nth, the matrix A (and in our case also B), consisting in the pairwise summation of each of these rows with the 1st row (the combined matrix in our case) multiplied by the coefficient m :; -but. / a 7.,. However, since in the combined matrix under matrix A there is a matrix-C, which is necessary to lead to a zero matrix, no permutation of rows of matrices C and D with rows of matrix A and B cannot be produced. As a result, the device selects the leading element among the elements of the 1st column of matrix A1 (at the ith step and the elimination process implements the elements of the 1st column of matrixes A1 and C, i.e. among the elements of the 1st column of the entire combined matrix I (i - 1,) "All signs of the row permutation are remembered and transmitted 1c between the modules as elements of the lower triangular matrix of permutations V fUj;} For (n-1), the Gauss algorithm step is zeroed out (n-1) of the columns of the combined matrices. However, to obtain the correct result, the nth column of matrix C. Therefore, in this case, the Gauss algorithm also has the nth step, which does not have the process of selecting the leading element (the aC element immediately becomes the leader, since there is nothing to compare it with), and the exclusion process is carried out similarly to the previous steps of the algorithm.

The receipt of the source data is organized as follows. At the 1st input of the device (i 1, p), each element of the i-th column of the combined matrix arrives, starting with the C element a (; and ending with Cp ;, at (n + K) -th input of the device (K 1 , K) - similarly, starting from the element Cc and ending dpK. In turn, the elements of the Kaedo column of the combined matrix are sent “to the corresponding inputs of the device with a shift by one cycle, i.e. the element goes to the 1st input of the device in 1– m cycle of his work, and the element - in (n + K) -th tact of the device.

eight

The device works as follows.

Put p 3, p M 2. It is assumed4- that the reception of information in all registers, including registers of blocks of deceleration, in D-triggers 25 and 36 of all computational modules is carried out on the falling edge of the clock pulse,

those. at the end of the cycle, and in all other triggers and the counter 46 - according to the front oron “sync pulse, i.e. at the beginning of the cycle, it is also conditional that the change in the state of the counters 23 and 41

r occurs on the positive, and counters .24 - on the negative signal drop at their decrementing inputs. We assume that before starting the calculations, the (t + 1) -th bits of all the registers of block 14.1 are set to the zero state (n is the size of the operands).

A start impulse arriving at the device launch input sets to

5 unit RS flip-flop 47, and also enters the selection input of the mode of the counter 45, into which the value (n + p-1) 4 is written, and through the OR element 48 to the input of the selection of the mode of the counter 46.

In the first clock cycle, on the leading edge of the clock signal, the counter 46 records information from the output of the counter 45, i.e. (n + p-1), the output of the negative transfer of counter 46 is zero, and the triggers 20.1 and 21.1 are also set to the D5 unit, after which the values (n-1) 2 and D-1) 0 are written to the counters 23.1 and 24.1. In addition, element a (and the initial matrix enters the second information input of module 1.1 and, having passed through switches 10.1 and 6.1, is written into the clock cycle in register 7.1 (the control inputs of both switches are units), and the unit from the trigger output

5 21.1 is written to the (t + 1) -th bit of P1 of block 14.1, at the inverse output of counter 24.1 is zero.

In the second cycle, the counter 46 decreases its value by one, at the outputs of the flip-flops 16.1, 20.2 and 21.2 there are ones, and at the output of the flip-flop .10

ra 21.1 - zero, element

12

 by

steps into the input of module 1.2 and writes to register 7.2, and unit c in 5–5 of the flip-flop 21.2 is written to the (TM) th bit P1 of the block 14.2, and "a goes through the switch 10.1 to the inputs of the switches 6.1 and 8.1 and comparison circuits 9.1, to other inputs

which comes a

tusg

", Ј

5 | a, | . Then the zero (UЈ, 0) from the output of the comparison circuit 9.1 (the sign of no row permutation) goes through the elements 18.1, 22.1 and the switch 19.1 (its control input has zero) to the control inputs of the switches 6.1 and 8.1, as a result a is overwritten in register

14

7.1 as well is recorded in P1 of block 14.1. In addition, the unit of the (m + 1) -th bit P1 of block 14.1 is rewritten into P2 of block 14.1 and appears at its output, is written to the trigger

25.1i appears at the input of the feature of permutation of the rows of module 1.2, counters 23.2 and 24.2 record the values (n-1) and 1, respectively, and the inverse output of the negative transfer of counter 24.2 is the unit that is there until the contents of the counter 24.2 will not become zero.

In the third cycle, the counter 46 decreases its value by one, at the outputs of the trigger 16.2.20 h 3.21.3 and 15.1, one appears, and at the output of the trigger 21.2 - zero, the element a enters the input of the module 1.3 and records the register 7.3, and the unit from the trigger output 21.3 - in (m + O-th bit P1 of the block 14.3, aL goes to the input of the module 1.2, because the output of the counter 24.2 is one, the switch

19.2 transfers to its output U2, 0, which is rewritten into register 25.2 and controls the operation of switches 6.2 and 8.2 so that it is written

in P1 of block 14.2, and a is "overwritten in register 7.2. In addition, a (arrives at the inputs of switches 6.1, 8.1 and comparison circuits 9.1, to the other inputs of which comes a ,,,,. Let

| a "| c (. Then the unit (U3 (from the output of circuit 9.1 is written to the trigger 25.1 and controls the switches 1 6.1 and 8.1), as a result, a is written to P1 of the block 14.1 (and rewritten to P2 of the block 14.1), and a51 is written to registers 7.1 and 5.1. In addition, the unit of the (t + 1) -th bit P1 of block 14.2 is rewritten in P2 of block 14.2, the output of counter 24.3 is one, counters 23.1, 24.1 do not change their state, since A single entry remains in the input (parallel information entry mode).

one)

one

7358681 °

In the fourth cycle, cmscnc 46 decreases its value by one, and in counter 41.1 is recorded (), one appears at the outputs of flip-flops 16.3, 34.1, 35.1 and 15.2, and at the output of flip-flops 16.1 and 21.3

Sh

15

25

 bt is fed to the input of module 2.1 and is written to register 31.1, and the unit from the input of trigger 35.1 is in the (t + 1) -th bit P1 of block 42.1, is fed to the input of module 1.3 and, since switches 6.2 and 8.2 receive 1) g , 0, is written to P1 of block 14.3, U 2, is written to trigger 25.3, and is overwritten in register 7.3. In addition, a 32 is fed to the input of module 1.2, and, since U 3 {1, is written in P1 of block 14.2, a al, - JQ in registers 7.2 and 5.2. In addition, the unit from (m + 1) -ro bit P1 of the block 14.3 is rewritten to P2 of the block 14.3, 1 - $ {is rewritten to the trigger 25.2, -C (supplied to the inputs of the switches 6.1 and 8.1 and, since the output of the AND 18.1 (regardless of the output of the comparison circuit 9.1) zero, -C (recorded in P1 of the block 14.1, and 2 through the switch 11.1 goes to the second input of the 4.1 multiplication-division block, by

Chit

 the first input of which comes from register 5.1, block 4 performs the division and the result n (is received in register 26.1, passed through switch 12.1 (on the element output).

35 OR 17.1 zero).

In the fifth cycle, the counter 41.2 is recorded (n − 1), the counter 46 decreases its value by one, its content becomes equal to zero and

40 its negative transfer output appears a unit that resets the trigger 47 to zero, and enters the decrementing input of the counter 45, reducing its contents by one.

,

) 45 and the same clock cycle at the outputs of the flip-flops 34.2, 35.2 and 15.3 is one, at the output of the flip-flops 16.2 and 35.1 is zero, b | u is fed to the input of module 2.2 and is written to the register 31.2, and 50 is the The (t + 1) th bit of P1 of block 42.2, b is fed to the input of module 2.1, and since Ugt 0 is written to P1 of block 42.1, Ugj is written to flip-flop 36.1, and b1 is rewritten to register 31.1. In addition, a, is fed to the input of module 1.3 and, since U s t, and is recorded in P1 of block 14.3 (and 23 is rewritten in P2 of block

55

eleven

14.3), a aL, is written to registers 7.3 and 5.3. In addition, U3 is rewritten to register 25.3, -CJ2 received at the inputs of switches 6.2 and 8.2, and since the output of element 18.2 is zero, is written to P1 of block 14.2, rewritten to P2 of block 14.2, and through switch 11.2 goes to block 4.2 which performs the multiplication to the second input of the adder

14.2, and re accepts- rewriting1

alz comes from a P2 block

, “The result of a 2 -ip t, At a 52

V2

 g

c in P1 of block 27.2, and it is written to register 26.2 (at the output of the element OR 17.2 one). In the same cycle, Cmc enters the inputs of switches 6.1 and 8.1 and is written to P1 of block 14.1, -C is rewritten to P2 of block 14.1, a j enters block 4.1, from which output the value

. -a (| / a Ј {m is taken to register 26.1.

, /

In the color cycle, counter 46 is recorded (n + p-2) 3 from the output of counter 45, triggers 21.1 and 20.1 are set to one and zero, respectively, the unit from the output of trigger 21.1 is recorded at the end of the cycle. (T + 1) -th bit g P1 of the block (similar to the first cycle), trigger 44.1 is set to one, and triggers 15.3, 16.3 and 35.2 are set to zero, fed to the input of module 2.2 and written to P1 of block 42.2, written to. trigger 36.2, b} is overwritten in register 31.2, bjj goes to input module 2.1 and (U 31 1)

recorded

to registers 31.1 and 29.1, and b14 - in P1

block 42.1, switches

 enters on entrances 6.3 and 8.3 and, since

at the output of the element And 18.3 zero,

recorded is written

in P1 of the block 14.3, in P2 of the block 14.3, gog {goes to block 4.3, which performs multiplication, on the second input of the adder 13.3 comes a | j and the result а2з + пг, "az a | 3 is taken in P1 of block 27.3- and tg is rewritten to register 26.3. In the same cycle, -C is fed to the input of module 1.2 and recorded in P1 of block 14.2, Cw is rewritten in P2 of block 14.2, m eaa {, arrives at block 4.2, which performs multiplication, at the input of adder 13.2 goes from P2 block 14.2, and the result is aja

27.2,

m

H2

a32

taken at P1

s.

block

 "I am i5

rewritten to register 26.2

735868

-WITH

ten

15

20

"

arrives at

12

block 4.1, output C "/ aeg a 4 {value of which

is transferred to register 26.1, -Cj is rewritten to P2 of block 14.1.

In the seventh cycle, similarly to the second cycle, the triggers 20.2, 44.1 and 21.1 are set to zero, the triggers - 44.2, 21.2 and 16.1 - to one the counter decreases its state by one (up to minus one), but on its inverse output remains zero, one sec trigger output 21.2 is written to (t + oh bit P1 of block 14.2, is fed to the input of module 2.2 and is written to registers 31.2, 29.2, a bf2 - block, b2i is rewritten to P2 block 42.2, U3 is washed down

flies to the trigger em on the input of the module in P1 of block 42.1

36.2, d entries recorded

in P2 of block 42.1),

2.1 (bjf is rewritten

m

2

 J

/four

repeat-

steps on multiplier 28.1, on

swarm adder input 39.1 enters b

 and the result is bЈ {+ I2 bj (b

is in P1 of block 40.1, a m

is coming

those -С

telny module

2

accept- overwriting the register 38.1. In the same way, $ 2 goes to the input of compute1.3 and is written to

five

five

0

five

0 P1 block 14.3,

sh

3f

enters the block

4.3, which performs multiplication, by

13.3 the result comes ATs + m-j, and | 3

adder input

N3

and

is accepted

in P1 of block 27.3, and rewritten in P2 of block 27.3, ha3 - into register 26.3. In the same cycle, -C is rewritten in P2 of block 14.2, m4 C / a goes to block 4.2, which performs multiplication, to the input of adder 13.2 comes from P2 of block 14.2 and the result C | a is received in P1 of block 27.2, and | is received in P2 of block 27.2, and | r from P2 of block 27.2 through switch 10.2 enters the inputs of switches 8.2 and 6.2 and is written to register 7.2, p4, rewritten to register 26.2, -C, steps 1 to block 4.1, from which the value of Cr, / ajf m $ (taken into register 26.1.

In the eighth cycle, the triggers 20.3, 21.2 are set to zero, the triggers 21.3, 15.1 are set to one, the counter 24.2 decreases its value by one, and zero appears on its inverse output, the unit from the output of the trigger 21.3 is written to (and + 1) - The th bit of P1 of block 14.3, dte is fed to the input of module 2.2 and is written to the P1 block

, 2, -2, .2,

B

m

42. g

42

42

28

39.2,

is accepted

13

rewritten into p2 block enters multiplier

 - to the second input, the summa result + m, - b, g b2 40.2,

m

rewrites the same d2j 2.1 cycle

r in this

in P1 block in the register 38.2. enters the input of module 2.1 and is written to P1 of block 42.1, d (is rewritten to P2 of block 42.1, goes to multiplier 28., to the adder comes LM and pH

the result of b b in PI block 40.1, ha in register 3S.1.

-4i

accepts L is rewritten. In the same tact, -Cg-j is rewritten in P2 of block 14.3, G4 enters block 4.3 which performs multiplication, by

four

R

four

"

the adder 13.3 arrives and the result, -ae5 is received in P1 of the block 27.3, a2 through

Uh

the switch 10.3 arrives at the inputs of the switches 8.3 and 6.3 and is written to register 7.3, t,

 41

rewritten to - in register 26.2,

register 26.3, ta5 | and also goes to block 4.2, which performs multiplication, to adder 13.2 comes-C and the result

 C22 is accepted rewritten via switch

. In P1 block P2 block 10.3 to + go5, - ase.

27.2,

27.2, a | g

steps on the inputs of a comparison circuit 9.2

where is compared with a | 2.

Let | a | r | | a | 2 | . Then the unit (J ™ 1 from the output of circuit 9.2 controls the switches 8.2 and 6.2 so that a | 2 is written to registers 7.2 and 5.2, and | g - to P1 of the block 14.2. In addition, counter 23.1 decreases its value by one, and the length of the block 14.1 becomes equal to one.

In the ninth cycle from the input of the module 2.2 is written in P1 of block 42.2, d, 2 is rewritten in P2 of block 42.2, from the output of adder 39.2 the result. b | z is received in P1 of block 40.2, raj, rewritten into register 38 .., is rewritten in P2 of block 42.1, from the output of adder 39.1

 1 - d4 accept- 40.1, and b | written to register 31.1, from the output of adder 13.3, the result -Cgj-Hn5 | "a, C | - is received in P1 of block 27.3, C, is rewritten in P2 of block 27.3, is taken in registers 7.3 and 5.3

result

is in P1 block

d "+ m4i b3i

H2 & M

a a | - in P1 of block 14.3, C is recorded in P1 of block 14.2, block 4.2 performs division, and the result -a | 2 / a | j is received in register 26.2

1735868

14

block tel

mmator b2

this

The modular block is spruce and is backed up to 4.3, on

R

four

"

prinirez

moves

mc at 26.2,

kotommator t +

1 block of block 3,

The single avlet is a and | 2 5.2, wow, che14 .1

mode42 .2, 42.2, tat in P1 in the roar of P2 39.1

Minimum and maximum sum, 7.3, 7.3, and 5.3,

letters .2 you- 26.2

ten

15

20

25

thirty

35

40

4S

50

55

is in P1 of block 40.2, b | matsa in register 31.2, p

In the tenth cycle, dg- is rewritten in P2 of block 42.2; from the output of adder 39.2, the result is d j d2, which registers with the register 31.2, P5 | rewritten to register 38.1, from the output of adder 39.1 the result is dZ (+ m5 (b91

is received in P1 of block 40.1, is written to registers 31.1 and 29. 1, Cfa - in PI of block 14.3, from the output of adder 13.3 the result a | + n) -jj. a2

B "

"

 AE

 but

"

is received in P1 of block 27.3,

block i 4.2 performs the division, and the result-, is received in register 26.2.

In the eleventh cycle from the output of adder 39.2, the result of da2 + mj | bja d2 is received in P1 of block 40.2, b | is taken in registers 31.2, 29.2, from the output of adder 39.1 the result b | (+ t $ r-b l b3 is received in P1 of block 40.1, d 41 is rewritten in P1 of block 42.1, a3 ,, - in P2 of block 27.3, С | 3 - in P1 of block 14.3, from the output of adder 13.3, the result a2 ,, CL is received in P1 of block 27.3, block 4.2 performs division, and the result mg-C | 2 / a | is received in register 26.2, m4g is rewritten in register 26.3.

In the twelfth cycle from the output of adder 39.2, the result is b2, + tsg egg

B | g

is received in P1 of block 40.2, rewritten in P2 of block 40.2, from the output of adder 39.1, the result is d + m42-b2 ,, d is received in P1 of block 40.1, (is received in P1 of block 42.1, from the output of adder.13.3 2. a2. Accepts a chap of block 27.3,

7.3.

ab

49

is accepted

P1 block 40.2,

output sms in P1 in the register

In the thirteenth cycle from the output of the adder 39.2, the value of d2t + m42- b | t d; L is received in d2, z - in P1 of the block 42.1, from the mator 39.1 the value of d2, "d | is accepted in P1 of block 40.1, b3n - into register 31.1, block 14.3 is reduced by one and becomes equal to zero (i.e., data is sent from its input to the output without delay), C3- is fed to the input of block 4.3, it performs There is a division, and the result of p43 / a33z is accepted in register 26.3.

In the fourteenth clock cycle from the output of the adder 39.2, the value d + mw bja "et dL is taken in P1 of block 40; 2,

1517

 - in register 31.2, block length 42. I becomes equal to zero, and from the output of adder 39.1 the value d-} f + +11143 b3c1 "is received in block P1

40.1.in register 37 AND appears on the first output of the device, С3гз is fed to the input of block 4.3 and the result

m 53 cge / a1z is accepted into register 26.3, and pce into register 38.1.

G n the fifteenth tact block length

42.2 becomes zero, from the output of adder 39.2, the value of C2 + ptsz L3eg. X1g is received in register 37.2 and appears at the second output of the device, is rewritten in P2 of block 40.2, from the output of adder 39.1 the value of d3 ь, X21 is accepted

register 37.1 and appears at the first output of the device.

In the last sixteenth clock cycle from the output of the adder 39.2, the value of d | 2+ + t, knots b3eg Xg is taken to register 37.2 and appears at the second output

devices. This completes the calculation of the elements of the resultant matrix X CA B + D. Thus, the total implementation time of the algorithm T n () / 2 + n (p + 1) + p + 2 + M-1 cycles, with the elements of the resulting matrix X being output to the device outputs the last p + M-1 cycles, and From the r-th output of the device, the r-th column of the matrix X (r 1, M) is inserted in the same way as the input elements of the matrices B and D to the corresponding inputs of the device. However, in the case of solving a stream of similar problems, the period of operation of the device is t T - - (n + M-1) cycles,. n () / 2 + p (n + И) + 11-1 cycles. This means that the first element a (the next unified matrix can be fed through t cycles after the element a has been fed to the previous combined matrix. In our case, T 16, t is 12 cycles, therefore, the elements of the next matrix can be started to be input to the device (together with the start pulse) from the thirteenth cycle.

Claims (1)

Formula of an Inventory Shadow A device for operations on matrices containing a synchronization unit and n computational modules (n is the order of the input matrix), each of which contains five triggers, two counters, two OR elements, a multiplication-division block, an adder, six com sixteen Q j 0 five 0 jc 40 e m mutators, two blocks of delay elements, three registers and an element, And the device's start input is connected to the synchronization block's same name, the output of which is connected to the synchronous input of the first computational module, the synchronization output, the row permutation sign output and the information output of the K-th computation the module (К 1, п-1) are connected respectively to the synchronous input, the input of the row permutation feature and the first information input. (К + 1) - the computing module, the second information input of the Р-th computing module (Р 1, p) is the Pm information input of the device, in each computing module the first and second bits of the sync input are connected respectively to the information inputs of the second and third flip-flops, the outputs of which are the first and second bits of the sync output of the computing module, input and the output of the sign of the permutation of the rows of which are connected respectively with the first information input of the sixth switch and the output of the fourth trigger, whose information input is connected to the output of the sixth switch a and the first input of the second OR element, the second input and output of which are connected respectively to the output of the third trigger and the combined control inputs of the first and second switches, the combined first information inputs of which are connected to the output of the second register and the first input of the comparison circuit, the second input of which is connected to the combined the second information inputs of the first and second switches and the output of the third switch, the control input of which is connected to the output of the second trigger and the inputs of the counting permission second and second counters, decrementingly the inputs of which are connected respectively to the zeroing inputs and setting the first trigger, the output of which is connected to the first inputs of the first OR element and the AND element, the second input and output of which are connected respectively to the output of the comparison circuit and the second information input of the sixth switch, the control input of which is connected to the output of the second counter and the second input of the first OR element, whose output is connected to the control inputs the fourth and fifth switches and the input of the block multiplication-division selection, the first and second information inputs of which are connected respectively to the outputs of the fourth switch and the first register, whose information input is connected to the information input of the second register and the output of the first switch, the first and second information inputs of the computing module connected to the first information inputs of the fourth and third switches, respectively, the second information inputs of which are connected respectively to the output The second and first blocks of the deceleration units, the control inputs of which are connected respectively to the output of the first counter and the device input P, the information output of the computing module are connected to the output of the third register, whose information input is connected to the output of the fifth switch, the first and second information inputs of which are connected to - responsibly with the first information input of the fourth switch and the combined first input of the adder and the output of the multiplication-division block, the output of the adder is connected to the info To the input of the first block of the delay elements, the inputs of the installation of the first and second counters are connected respectively -1 to the inputs n-1 and P-1 of the device, characterized by a heme, in order to extend the functionality by calculating expressions of the form X CA G- + D in the mouth The algorithm introduced M computational modules (M is the number of columns of matrix B), each of which contains a multiplier, adder, two blocks of delay elements, a counter, an OR element, four flip-flops, four registers and two switches, the synchro-input, a sign of the row permutation and the first Inputs r-th computing module (r n + 1, m + M) are connected to the same outputs (r-1) of the computing module, the second information input and output of the r-th computing module are respectively (n + + d) -m information input and r-th exit oystva, in each i-th computing unit and the first bits of the second clock terminal connected respectively to the data inputs of the first and second flip-flops, the outputs of which are respectively jrep 0 five output and second bits of the output of the syncronization of the computing module, the input and output of the permutation feature of 5 lines of which are connected respectively to the information input and output of the third trigger, the first information input and output of the computing module are connected respectively to JQ information input and output of the fourth register, the second information input and output of the computational module are connected respectively to the first information input of the third the switch and the output of the third register, the information input of which is connected to the output of the adder and information input of the first block of delay elements, the output of which is connected to the second information input of the third switch, the output of which is connected to the combined first information inputs of the first and second switches, the combined second information Formation inputs which are connected to the output of the second register, the information input of which is connected to the output of the first switch and the information input of the first register Stra, whose output is connected to the first input of the multiplier, a second input and whose output is connected respectively to the data input of the fourth register and the first input of an adder, whose second input is connected to the second 5 to the output of the second block of delay elements, the first and second information inputs of which are connected respectively to the outputs of the second trigger and the second switch, the control input of which is connected to the control input of the first switch and the output of the OR element, the first and second inputs of which are connected respectively to the information input of the third trigger and the output of the second trigger, the output of the first trigger is connected to the control-. To the third input of the switch on the counter resolution input, the output of which is connected to the control input of the second block of delay elements 0 0 ki, the first output of which is connected to the information input of the fourth trigger, the output of which is connected to the sync code of the first register and decrement input of the counter, the installation input of which is connected to the input of the (n-1) th device, the control input of the first block of delay elements is connected to the input P device. . W C