SU1734234A2 - Device for detecting moving objects - Google Patents

Abstract

The invention relates to television technology and can be used to detect moving small objects. The purpose of the invention is to expand the functionality by determining the coordinates and time of detection of small moving objects against moving objects. A device for detecting moving objects comprises a transmitting television camera 1, a threshold unit 2, the first and second elements AND 3, 4, the memory block 5, the first, second and third elements OR 6, 7, 8, the first second, third D-flip-flops 9 , 10.11, first, second pulse generators 12, 13, shaper of horizontal and personnel pulses 14, first and second frequency dividers 15, 16, first and second counters 17, 18, key 19, first, second, third, fourth, p pulse counters 20-24, delay element 25, memory block 26, comparison circuit 27. 1 Il.

Description

The invention relates to a technique of television and can be used to detect small objects against the background of moving objects.

The purpose of the invention is to expand the functionality of the device by determining the coordinates and time of detection of small moving objects on the background of moving objects.

The drawing shows a block diagram of the device.

The device contains a transmitting television camera (PTC) 1, a threshold unit 2, the first and second element And 3, 4, the memory block 5, the first, second, third element OR 6,7, 8, the first, second, third triggers 9,10 , 11, first and second pulse generator 12, 13, shaper of horizontal and personnel pulses 14, first and second frequency dividers 15, 16, first and second

counters 17, 18, key 19, first, second, third, fourth, fifth pulse counters 20-24, delay element 25, random-access memory unit 26, comparison circuit 27.

A device for detecting moving objects operates as follows.

In a similar state, the D-flip-flops 9, 10, 11, which form the shift register, are in the zero state. The pulse counters 20-24 are reset. Pulse generators 12, 13 are disabled. Key 19 is open. The memory unit 26 is in the initial state.

When the device is turned on, the first pulse generator 12 is started, from the output of which the sampling pulses are fed to the input of the imaging unit 13 horizontal and frame pulses, to the input of the second frequency divider 16 and to the input C of the memory unit 5.

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Lower pulses from the first output of the imaging unit 14 are fed to the input of the first frequency divider 15, to the installation input of the second counter 18, to the first input of the PTC 1 and to the zero input of the fourth pulse counter 23, it has encircled it. The frame pulses from the second output of the imager are fed to the zeroing inputs of the first 20 and third 22 pulse counters, wrapped them, to the installation input of the first counter 17, to the counting inputs of the second 21 and fifth 24 pulse counters, where they are counted, to the second input of the PTC 1, Gating inputs C of the first 9, second 10 and third 11 triggers. The pulses from the output of the first frequency divider 15 are fed to the first input of the second element OR 7, from the output of which they pass to the counting inputs of the first counter 17 and the third pulse counter 22, where they are counted. The pulses from the output of the second frequency divider 16 are fed to the counting inputs of the second counter 18 and the fourth pulse counter 23, where they are counted. The current value of the raster line number from the output of the third pulse counter 22 is fed to the third input of the RAM, the second input of which receives the current value of the element number in the raster line from the output of the fourth pulse counter 23. When the beam PTC 1 moves along the line, the sampling pulses through the second frequency divider 16 to the second counter 18, the state of the latter is changed every K of pulses, where K is the division ratio of the second frequency divider 16. The line is thus divided into sections, each and Which corresponds to a certain state of the second counter 18. The same happens when the beam moves during a vertical sweep.

The frame is divided into horizontal stripes using the first frequency divider 15, which has a division factor and the first counter 17. As a result, the entire raster is divided into rectangular sections, each of which corresponds to a certain state of the counters 17 and 18 and a certain cell of the memory block 5 and, when each such section passes by the sweep beam, the address of the cell corresponding to this section is set at the address inputs of the memory block 5, the output signal (the current frame sync pulse) is second the first pulse output pulse counter 21c in the parallel code goes to the second input of the comparison circuit 27, the first value of which receives in the parallel code the current value (so far equal to zero) from the output

the first pulse counter 20. If the code at the first input of the comparison circuit 27 is not larger than the code at its second input, then a signal is generated at the output of the comparison circuit 27

high level 1. Otherwise, a low level O signal is generated. The output signal of the comparison circuit 27 is fed to the control input of the key 19. In this case, the single signal from the output of the comparison circuit 27 opens the key 19, and the zero signal does not change the open state of the key 19. The output signal (the current frame number) of the fifth pulse counter 24 is fed to the first input of the RAM block 26. The output 5 signal of the PTC 1 is fed to the input of the threshold block 2.

The trigger signal is fed to the input of the delay element 25, where it is delayed by the time Tk and to the setup input S of the first

0 D-flip-flop 9, throwing it to 1. This signal 1 is fed through the third element OR 18 to the information input of the second D-flip-flop 10.

The next (first) frame sync5 pulse sets 1 second D-flip-flop 10 and resets the first D-flip-flop 9 to О, zeroes the first 20 and third 22 pulse counters, returns the first counter 17 to the initial state, increases by one

0 the current value of the second 21 and an additional 24 pulse counters. After some time from the output of the delay element 25, the delayed signal is triggered at the zeroing inputs of the second 21 and fifth 24 counters.

5 pulses, threw them, and to the control input of the second pulse generator 13 and starts it. Clock pulses from the output of the second pulse generator 13 are received at the information input, the key 19 and

0, the counting input of the first pulse counter 20, where counted. Since the current value of the second pulse counter 21 is 0, a high level signal 1 is generated at the output of the comparison circuit 27,

5 so that key 19 opens and transmits clock pulses from the output of the second pulse generator 13 to the second input of the element OR 7. Since simultaneously these pulses arrive at the counting input of the first pulse counter 20, where it is counted, only the second input of the element OR 7 passes one clock pulse, after which a low level signal O is set at the output of the comparison circuit 27, and

5, therefore, key 19 is closed. As a result, the sweep of the cells of memory unit 5 begins with the second row. The high level 1 signal from the direct output of the second D flip-flop 10 passes through the first element OR 6 to the recording control input and holds the memory block 5 in recording mode. At the same time, the information input P of the memory block 5 is fed O from the inverse output of the second D-flip-flop 10. This same signal, received at the first input of the second element 4, blocks the operation of this element. Thus, all cells, starting from the second line, are written O, i.e. clearing the memory block 5.

Claims (1)

Apparatus of the invention for detecting moving objects according to Aut. No. 1385331, characterized in that, in order to expand the functionality of the device by determining the coordinates and time of detection of small-sized moving objects against moving, the second and third elements OR, the second generator pulses, a key, five pulse counters, a memory unit, a delay element, and a comparison circuit, the first output of the horizontal and frame pulses connected to the zeroing inputs a pulse counter, the counting input of which is connected to the output of the second frequency divider, the second output of the horizontal and vertical pulses is connected to the reset input of the first and third pulse counters, the output of which is connected to the third input of the RAM, the second input of which is connected to the output of the fourth pulse counter, and with counting inputs second and fifth pulse counters, the output of which is connected to the first input of the RAM unit, the control input of which is connected to the output of the second AND element, the output of the first frequency divider is connected via the second OR element, the second input of which is connected to the output of the key, the control input which is connected through a comparison circuit with the output of the first pulse counter, with a counting the inputs of the first counter and the third pulse counter, the setup input of the first D-flip-flop is combined with the input of the delay element, the output of which is connected to the control input of the second pulse generator, the output of which is connected to the information input of the key and the counting input of the first pulse counter, and zeroing inputs the second and second counters, the first input of which is connected to the second the input of the comparison circuit, the second output of the second pulse counter is connected to the second input of the third OR element, which is installed between the output of the first D-flip-flop and the information input of the second D-trigger.