SU1734106A1 - Device for digital filtering with controlled gain - Google Patents

Abstract

The invention relates to filtering devices and can be used in devices and systems for the digital processing of random signals in a wide dynamic range. The aim of the invention is to improve the accuracy and enhance the functionality by measuring the energy performance of a signal. The input signal is fed to the input of the multiplier 1, to the second input of which a correction factor is applied from the output of the register 12. The value of the multiplier is automatically set so that the filtering and non-linear conversion operations are performed in the working range of the blocks. The output signal of the multiplier is fed to the input unit 2 digital filtering. The filtered signal is fed as an integral part - the sign and the mantissa - to the information output Y of the device and through the fixed coefficient memory block to the input of the dividend dividing unit 4. The division of the signal at the input of averaging block 5 by the correction factor eliminates transients at the output of this block when the multiplier changes discretely and makes the measurement scale at the device output Z unchanged and at the second inputs of the first and second groups of K (2K - number of levels) blocks 6 compare. Blocks 6 together with the first and second groups of elements NOT 7, the first 8 and second 9 groups of elements AND, element OR-NOT 10, element 11 and 11, delay element 13 and block 14 of the permanent memory form a correction factor at the output of register 12 as the numbers (nj is an integer) in the hysteresis dependence on the energy characteristic. From the output of the fixed memory unit 15 connected by the input to the register 12, the code of the number ni, which is a floating-point binary code of the true value of the filtered signal, is output. 1 il. (L s x | cj io o

Description

The invention relates to digital signal processing and can be used in digital processing systems for random processes in a wide dynamic range.

In digital processing devices to expand the dynamic range

the filtered signal use gain control in digital filters. In this case, the expansion of the dynamic range is achieved without increasing the digit size of the digital filter and, therefore, without significantly increasing the dimensions of the processing device.

The purpose of the invention is to improve the filtration accuracy and enhance the functionality.

A device for digital filtering with adjustable transmission coefficient is known. This device contains a digital filtering unit that includes a memory unit, the input of which is the information input of the device, a multiplier, an accumulator, and a coefficient setting unit. A comparison unit is connected to the digital filtering unit, to the second input of which the output level sensor is connected. The output of the comparison unit is connected directly to the first input and through the element NOT to the second input of the accumulating adder. The output of the accumulating adder is connected to the input of the control of the transmission coefficient of the digital filtering unit and through the shift unit to the third input of the accumulating adder.

In this device, the change of the correction factor, which controls the transmission coefficient of the filtering unit, is made according to a special rule that ensures the independence of the time constant of the transition process of the correction factor from the magnitude of the signal jump at the device input. This somewhat reduces the distortion of the filtered signal. However, the distortion of the waveform in this device is still significant, and the distortion is related to the dynamics of the correction factor.

The essence of the invention is that the increase in filtering accuracy and further non-linear signal conversion, achieved as a result of the elimination of continuously flowing transients, is realized by abruptly changing the correction factor when the energy characteristic of the filtered signal reaches the threshold values. At the same time, the change or the preservation of the current value of the correction factor upon reaching this threshold is made dependent on the history of the current value of the energy characteristic, this dependence being chosen to be hysteresis. The number of N values and the difference of the corrective values are RI

common multiplier

- represented in

Ri +1

as an integer of 2, and the number of 2K threshold levels are defined by the following formulas:

N-ai3 + o. G.n.-nil, (1)

2K 2 (N-1) J

where Odiap is the dynamic range of the input signal, dB;

Of - the dynamic range of the block

digital filtering, dB;

OD is the dynamic range of the hysteresis loop (the ratio of the loop width to the left i threshold), dB;

 - designation of the integer part of a number,

enclosed in brackets.

To preserve the scale of the filtered signal, the latter is represented by a floating point code, the sign and the mantissa of which is removed directly from

a digital filtering unit operating with a fixed comma, and the order is determined by the degree of the number 2 of the current value of the correction multiplier, taken with the opposite sign. To preserve the scale of the energy characteristic, eliminate jumps at the input of the averaging block and the transients at the output of the averaging block corresponding to these jumps, simultaneously with changing the correction factor, divide the current value of the signal at the input of the averaging block by the value of the correction factor for the modulus signal or by the square factor value quadratic

signal conversion; Thus, spasmodic changes in the correction factor, expanding the dynamic range of the digital filter and non-linear converter, do not cause

changes in the filtered signal and its energy characteristics. The proposed organization of the digital filtering device allows to extend its functionality by issuing

continuously measured to solve the main problem of the energy characteristics of the filtered signal.

The drawing shows a block diagram of the proposed device.

In the drawing: multiplier 1, digital filtering unit 2, coefficient constant memory unit 3, division unit 4, averaging unit 5, comparison units b, elements HE 7, elements AND 8, 9,11, element

OR-NOT 10, register 12, delay element 13, blocks 14, 15 permanent memory; X - information input device; T is the clock input of the device; - AI - the inputs of the task of constants; Y is the output of the filtered signal, Z is the output of the energy characteristic of the signal.

The device works as follows.

The input signal, represented by a binary code, is fed to the input of multiplier 1, the second input of which is supplied with a correction factor from the output of register 12. The value of the correction factor is automatically set so that filtering and nonlinear conversion operations are performed in the working dynamic range of the corresponding blocks. The output signal of the multiplier 1, which is the product of the input signal and the correction multiplier, is fed to the input of the digital filtering unit 2. The operation of block 2 is clocked by the frequency of the clock signal coming from the clock input device. During the clock period, the digital filtering unit 2 filters the next value of the input signal. The filtering is performed in accordance with the rule of cascade implementation of, for example, digital recursive filters with second-order elementary links.

The filtered signal from the output of digital filtering unit 2 is fed as an integral part to the output Y of the device and to unit 3 of the permanent coefficient memory, which performs nonlinear signal transformations. Nonlinear conversion provides a calculation of either the variance or the modulus of the signal. In the first case, in block 3, a quadratic function is implemented, and in the second, a function of the signal module. The converted signal is fed to the input of the dividend block 4 division. The second input of block 4, the divider input, receives the value of the correction multiplier. The division signal at the input block

Averaging a correction factor eliminates transients at the output of this block when the multiplier changes in steps and makes the measurement scale of the energy characteristic unchanged. The signal proportional to the energy characteristic comes from the output of block 5 averaging to the second inputs of the blocks

6 and to the output Z of the device (output of the energy characteristic) for use as an additional result in the tasks of analyzing the energy properties of the input signal.

The device realizes the formation of a correction factor in hysteresis depending on the current value of the energy characteristic according to the following rule:

RrHnpHAi Zn A2; A3 Zn A4., A2k-1 Rl with Zn Ai; R2 with Aa Zn Az;

Rrf

(2)

R2k-2 with A2k-2 Zn 2m-i; R2k-1 with A2k Zn.

Such a law of forming a correction factor eliminates the possibility of its oscillations occurring at characteristic values close to threshold levels.

The formation of the correction factor Rn (when) is as follows.

The threshold values Ai, A2, Az, Az are fed to the inputs of the comparison block 6. The current inputs go to the second inputs of these blocks.

the value of the energy characteristics of the filtered signal Zn. If Zn Ai, then the output of block 6i is a signal of a logical unit, which is fed to the first input of block 14 of the memory. AT

block 14 at address 100, the value of the multiplier RL is flashed. At the same time, the output of the element 11 is a pulse for writing the multiplier RI to the register 12. This pulse is formed as follows. Signal

the logical unit at the output of element 6i is inverted by element HE 7i. A logical zero at the output of the element NOT 7i causes the appearance of a logical zero at the output of the element AND 8i AND (at the input of the element IL AND-NOT

ten). At the second input of the element IL AND-NOT 10 is also a logical zero. Logical zeros at the inputs of the element IL AND-NOT 10 lead to the appearance of a logical unit at its output. Unit level at the input element I11

is allowing the clock pulse to pass to the second (control) input of register 12. The delay introduced by delay element 13 provides a clock pulse to be written to register 12 at the moment when the information on its first input is already established. Similarly, corrective factors are formed at A2 Zn Az and at A Zn. In the case when Ai Zn A2, the outputs

elements of 6i and 62 comparisons simultaneously appear logical zero signals. These signals cause logical units at the outputs of the elements 7i and 72, a logical unit at the output of the element And 8i, logical

zero at the output of the element OR NOT 10 and the inhibitory potential at the input of the element 11. The clock pulse does not pass to the control input of register 12, the recording is not made, and in register 12 remains

the previous value of the correction factor Rn-h. Similarly, the blocks work at AZ Zn A4.

Thus, the required law of the formation of a correction factor is maintained, the value of which is stored in register 12 during one operation cycle of the device, and depending on the value of the energy characteristic of the filtered signal, changes or remains equal to the previous value.

The value of the correction multiplier Rn from the output of the register 12 is fed to the address input of the constant memory element 15. In the cells of the block 15 with the addresses corresponding to the multiplier values, binary codes of degree 2 of this multiplier are stitched, but taken with a reversed sign (if Pi 2 °, Pa, Pz, then the codes O, P, r are flashed in the cells These codes determine the floating point binary order of the true value of the filtered signal, the sign and the mantissa of which are removed from the digital filtering unit 2, independent of the current value of the correction factor. The output of the unit 15 together with the unit output. digital filtration composition L y output device.

Thus, the device improves the accuracy of filtering a signal that changes in a dynamic range that exceeds the dynamic range of the filter. This is achieved by eliminating transients in the filtered signal by discretely changing the correction factor, automatically taking into account the current scale of the filtered signal, excluding fluctuations in the correction factor in the vicinity of the transition points by using a hysteresis characteristic, and also eliminating transients in measuring the energy characteristic of the input signal used in generating corrective multiplier. In addition, the functionality of the device is expanded — simultaneously with the filtering of the signal, the device measures the energy characteristic of the input signal.

Claims (1)

A digital filtering device with an adjustable transmission coefficient, comprising a multiplier and a digital filtering unit, the information input of which is connected to the output of a multiplier, the first input of which is the information input of the device, the clock input of which is a clock input of the digital filtering unit, characterized in that In order to increase accuracy and enhance functionality by measuring the energy characteristics of the signal, a fixed memory units, division block, averaging block, first and second groups of K (2K is the number of levels) of comparison blocks, first and second groups of K elements NOT, first group of K elements And, second group of K-1 elements And, element OR - NOT, register, AND element, delay element and two permanent memory blocks, with the output of the digital filtering unit connected to the address input of the constant coefficient memory unit, the output of which is connected to the first input of the division unit, the output of which is connected to the information input of the unit averaging whose output is the output of the energy characteristics of the device and is connected to the first inputs of the first and second groups of the comparison units, the outputs of which are connected to the inputs of the corresponding elements NOT respectively the first and second groups, the outputs of which are connected respectively to the first and second inputs of the corresponding elements AND of the first group whose outputs are connected to the corresponding the inputs of the element OR-, whose output is connected to the first input of the element AND, the output of which is connected to the clock input of the register, the output of which is connected to the address the input of the first memory block, the second inputs of the multiplier and the division block, the output of the i-th (i 2, K) comparison block of the first group is connected to the first input of the (I) -th element AND of the second group whose output is connected to the i-th address the input of the second block of permanent memory, the output of which is connected to the information input of the register, the output of the j-th Q 1, K-1) of the comparison unit of the second group is connected to the second input of the j-ro element AND of the second group, the output of the first comparison unit of the first group and K-th unit of comparison of the second group are connected respectively to the first and ( +1) -th address inputs of the second block of the permanent memory, the second input of the And element is connected to the output of the delay element, the input of which is connected to the clock input of the averaging block and connected to the clock input of the device, the information output of which forms the output of the digital filtering block and the output of the first the fixed memory unit, and the second inputs of the comparison unit of the first and second groups are inputs for setting the constants of the first and second groups of the device, respectively.