SU1164661A1 - Adaptive control system for objects with varying time lag - Google Patents

Description

The invention relates to the automation of technological processes with varying delay and can be used, in particular, for the automation of thermal power plants.

• Adaptive 'control system is known for objects with varying delay, containing series-connected master, comparing, element, controller, object and serially connected predictor and model with adjustable delay, connected by the input to the second input of the comparing element, and output to the third input of the comparing an element whose fourth input is connected to the output of an object connected by an input to the founder's input of £ 13.

The disadvantages of this system are a decrease in the system performance with an increase in the object lag and a decrease in accuracy due to the need to reduce the controller's transmission coefficient with an increase in the object lag.

Closest to the proposed is an adaptive control system for objects with variable delay, containing serially connected master, comparing element, regulator, object, block for determining delay, regulating unit and model with adjustable delay, connected by output to the second input of the comparing element, predictor, connected an input with a regulator output, and an output with a second input of the model with an adjustable delay and a third input of the comparison element, the fourth input of which connected to the output of the object, wherein the delay determining unit comprises first and second formers, the first and second flip-flops, counter decoder ^., dial delay and · controlled reference oscillator C23.

I

However, the known system is characterized by an insufficient accuracy of modeling the lag time, and the limited range of its change. The first circumstance is connected with the fact that the usual form of approximation is the preliminary decomposition of the “frozen” transfer function of the model with an adjustable

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lag in rapidly converging rows and the restriction of a small number of members of the series. Approximation errors with this method of implementing a block with 5 adjustable delay increase with an increase in the rates of change of variable decomposition coefficients caused by an increase in the rate of change of the value of delay.

10 This in practice leads to the following limitations: slow changes in the lag time are considered, 'lag time adjustment is considered for small ranges of its deviations from the required optimal values, the simpler statistical quality criteria are selected in a theoretical analysis of the system as a whole.

20 The limited range of latency variation in the model with adjustable delay does not allow to apply the known system without significant additional error in the case when the delay time varies in a significant range - from tens of seconds to tens of minutes, although the delay time is set by the delay determination unit with sufficient degree of accuracy. The use of a known system in such cases is possible only when the structural scheme of the model with adjustable delay is changed.

The purpose of the invention is to improve the accuracy and the expansion of the field of application of the system.

This goal is achieved by the fact that, in an adaptive control system for objects with variable delay, containing a serially connected master, a comparing element and a regulator connected by an output to the input of the control object, a delay determining unit, a predictor connected by an input to the output of the regulator, and an output A shaper is inputted to the second input of the comparison element 50, the third input of which is connected to the output of the control object and the first input of the lagging definition unit United analog to 55 digital converter, memory. device and digital-to-analog converter, serially connected binary address counter, and

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a decoder, the first output of the delay detection unit is connected to the control inputs of the binary address / / counter counter, and the form-, · rover ', digital-analog output $

the converter is connected to the first input of the delay detection unit, the output of the decoder is connected to the information input of the binary address counter, the outputs of the generator 10 are connected respectively to the read-write inputs of the storage device, the second output of the delay determination unit is connected to the second decoder input, the output of the duplicate-15 The address of the address counter is connected to the control input of the memory device, the output of the digital-to-analog output. the converter is connected to the fourth input of the comparison element M and the input of the analog-digital converter is connected to the output of the predictor.

FIG. 1 shows a block diagram of an adaptive regulatory system; in fig. 2 is a block diagram 25 of a lag detection unit; in fig. 3 - functional diagram of the decoder.

The system contains setpoint 1, comparing element 2, regulator 3, ' ₃ &

control object 4, delay detection block 5, predictor 6, driver 7, analog-to-digital converter 8, memory 9, digital-to-analog converter ··, receiver 10, address counter 11 and decoder .12.

 Predit.el 6 can be made in the form of serially connected integrators, the number of which is determined by the form of its transfer function. Blocks 7-10 form a model 13 with an adjustable lag. ''

Blocks 11 and 12 form a control block 14. .

Block 5 determining the delay contains the second amplifier 15, the second trigger 16, the first amplifier 17, the first trigger 18, the second decoder 19, the counter 20, the unit 21 of the delay and controlled oscillator 22 of the reference frequency (UGOCH).

35

45

50>

The decoder 12 contains η elements 23 (n is the number of digits) of the bitwise coincidence of two numbers A and B, η elements 24 of the bitwise ^ coincidence of the negation of these numbers A and B, η of OR elements 25 and element 26 of the multi-input coincidence circuit. Elements 23, 24, and 26 implement logical type I operations.

Shaper 7 is used to receive two pulses of a certain duration: “Reading” - “Record” shifted relative to each other, in response to each pulse received at its input from the output of the reference frequency of the delay detection unit 5. At the same time, the pulse from the output of the reference frequency unit 5 changes the state of the binary counter 11 of the address of the control unit 14, preparing the next address of the charger, on which the read-write operations should be performed).

The following requirements are imposed on the “Read” and “Write” pulses:

> T _a

^ TSOS ⁴ T Th

where t

^x sn T

Thu ^x zp

- respectively, the duration of the read and write pulses in

> Memory, recording in the DAC

and circulation in memory.

The decoder 19 is designed to decipher the status of the triggers 16 and 18, as well as to generate control signals "Addition" or "Subtraction" of switching modes of the counter 20 and the controlled oscillator 22 of the reference frequency ("Inhibition" or "Enable" generation) according to the following table.

__ Trigger "" {"Control signal

______

0 0 "Disabling generation 22"

0 1 "Addition 20" "Generation resolution 22"

1 0 "Subtraction 20" "Generation resolution 22"

1 1 "Prohibition of generation 22"

The first amplifier 17, connected to the output of the object 4, and the second amplifier 15, connected to the output 55 of the Model 8 with an adjustable delay, in addition to the amplification, filter the input signals.

5 6

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The decoder 19 can be implemented as a chip K155IDZ.

UGOCH 22 serves to generate timestamps in the form of reference frequency signals and has two outputs. The first output connected to the counting input of the counter '20 is controlled by the decoder 19. The second output connected to the binary counter 11 of the address of the control unit 14 and the input of the Model 13 driver 7 with an adjustable delay represents the output with continuous generation. The signals of the reference frequency of the first output are used in determining the delay time, the signals of the second output are used to synchronize the operation of the control unit 14 and the model 13 with an adjustable delay in accordance with the code, the delay time in the counter 20.

The beginning of the change of the signals at the outputs of the object 4 and model 13 is determined respectively by using amplifiers 15 and 17, 'which form the switching threshold potentials for the flip-flops 16 and 18 with virtually no delay. Moreover, if the trigger 18 is set first in one state, then A _m <%, if

it is set second, where 7 is the time, lags, 0 is the object, m is the model.

In the first case, the signal from the second output of the decoder 19’s counter 20 'is set to addition mode, the ban is lifted from UGOCH 22 and an additional number of pulses is entered into counter 20 proportional to the difference%. Generation

The UGOCH 22 is terminated when the trigger 16 is set to one ,. since with the fourth output of the decoder 19 it receives a inhibitory signal.

In the second case, the counter 20 is set to the subtraction mode by the signal from the third output of the decoder 19, while the pulses are subtracted from the contents of the counter -20 implemented in a similar way dependency.

Thus, in the counter, block 5 for determining lag measures the magnitude of the lag of an object by the formula

ten

15

20

25

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where - the value of the delay set by the operator in the counter 20 through the setting device 21 before starting work;

(p-1)

and (n) - denote the previous and

the next cycles of adaptation.

The control unit 14 is designed to generate a sequence of addresses (starting from the first) for a memory device 9 of model 13 with adjustable delay. The number of generated addresses depends on the time lag.

which is stored in the counter 20 of the block 5 definitions delay, and is expressed through

n = 2 ^Ky = X / (3)

where K _th - the Number of digits of the counter 11 addresses to place the code ί '

n = number of addresses or the current recalculation factor of the binary counter 11 addresses.

The maximum number of generated addresses depends on the maximum possible lag of the object, i.e. is determined by the value ΐ ΪΙ _{) ΪΙβχ} .

35 FIG. 1 the following notation is entered: Xp - regulating effect; X - adjustable value;

X _RS , X _axis and X _OSG - respectively, the main feedback signal, the signal

40 inertia compensation and delay lag signal; op is the operator.

The principle of anticipation of delay and compensation of inertia with adaptive high-precision time tuning is the basis for building an adaptive regulation system with variable delay.

₅₀ lags in a wide range of its change.

It is known that a complex object, in particular heat and power, with ₅₅ dos tatochnoy degree of accuracy can be approximated with the transfer function N ₀ (p) _{of the} AND type =

ρίο -ρΐ.

V = ₇ _____ "_ Lo £ -_ ₍₄₎

⁰ Tt _о p +1) (ό _β ρ + 1) T'r + 1

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where k

o 'o' yo _o and t '

T „=

- respectively, the gain, large, smaller and equivalent constant time of 5 object 4 ’

- lag time;

^t about ⁺ ^ 'about ·

Then the transfer function of the predictor 6 will be written in the form of K

^{= t} aP

where the gain and the equivalent time constant of the predictor is 6 15

equal to the corresponding parameters of the object 4.

The transfer function of the model 13 with adjustable delay is defined as

tm _ F (S H

* HE Ρ + Ϊ) "

, (6)

where is the lag time of the model. The total transfer function of series-connected predictor 6 and model 13 with adjustable delay is the transfer function of the full object model, i.e.

(7)

When X * (p)

X * = xG _with =

X * C1 = X * M ₆ m # - V +

u * = ^A OS2

ten

20

25

P ^ m

X *

Latency is the most important parameter of an object with a known value of the gain. Violation of condition (12) not only leads to a decrease in system performance, but may cause instability in operation. Therefore, the important conditions for performing (12) is the adaptation of the system to changes in the object lag time, which, in particular, for heat and power processes can vary from tens of seconds to several minutes when the load and state of the object change over time during operation.

Adaptation of the system in accordance with condition (12) can be achieved with accurate determination of the delay time and accurate installation in the model when it is changed over a wide range.

The system works as follows.

In the initial state, the adaptive control system made a test of the task coming from setpoint 1 ,. In this case, in block 5 for determining the delay, the code for the delay time is fixed for the model 13 with adjustable delay. This code sets the operation cycle of the control unit 14, which generates the address set for the storage device 9 of the block 13 using the binary counter 11 of the address and the decoder 12.

As a result, in each cycle, at the address formed in binary counter 11, the shaper 7 reads information related to the time (s ^ · £ _m ), which through the digital-to-analog converter 10 is fed to the second (summing) input of the comparing element 2 At the end of the reading, a new information is written to the storage device at the same address, coming from the output of the predictor 6. through the analog-to-digital 'converter 8. At the next'

; pulse output frequency reference

block 5 determining the delay

similarly on the next

(eight)

(9)

(ten)

and (9) is

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The condition of equality is a condition of anticipation of delay and compensation of inertia. It will take place subject to

(eight)

35

 Woo = Hom

(eleven)

From (11), taking into account (5), we obtain that condition (11) is satisfied if

B = (12)

It follows that if the condition (12) for the system is satisfied, then the delay is taken out of the closed control loop and the response of the system at the output becomes delayed. This ensures that the system can operate with maximum speed, as if there were no lag. In this case, the parameters of the regulator can be calculated by a known compensation method for systems without delay, in which.

40

45

50

K = T® p 2K ₀ 6

(13)

55

t; , (and)

where Кр and T _и are the gain | and the PI-controller isodrome time.

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new address is read information related to the point in time

-G ") +% l}, etc., to [(^ ⁺ 1 - 6" then the next (s · + 1) -th cycle begins. ₅

The next adaptation cycle is carried out at each change by the operator of the task, either through setpoint 1, or when a trial single impulse is applied. The block 5 for determining the delay ίο, according to the description of its work, determines the change in the values of _β-β , and a new value of the delay time is recorded at its information output if the characteristic of the object has changed. This in turn leads to a change in the current conversion rate of the binary counter 11 addresses, and hence the time ΐ _"Μ.

The operation of the control unit 14 and the model 13 with adjustable delay remains similar.

Thus, changing the design of the control unit 14 and model 13 with adjustable delay of the known system and introducing new functional connections between the blocks that synchronize their work with the delay detection unit can significantly improve the accuracy of the system and expand its functionality, and hence the scope. The lag time in the model 13 is reproduced in the proposed system in exact accordance with the lag time obtained in the lag determination unit, and the range of the lag time is unlimited.

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Addresses and Formations> 7

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iika 3 addresses

Fig.Z

Claims (1)

ADAPTIVE CONTROL SYSTEM FOR OBJECTS WITH VARIABLE DELAY comprising serially connected dial comparing element and a controller, coupled output to the input of the control object determination unit lag predictor coupled input to an output controller, and output - with a second input of the comparing element, the third input of which connected to the output of the control object and the first input of the lag detection unit, characterized in that, in order to improve the accuracy and expand the scope of the system, a shaper and serially connected analog-to-digital converter are introduced into it ,; a memory device and a digital-to-analog converter, a serially connected binary address counter and a decoder, the first output of the delay determination block is connected to the control inputs of the binary address counter and driver, the output of the digital-analog converter is connected to the first input of the delay definition block, the output of the decoder is connected to the binary counter information input addresses, shaper output are connected respectively to the write / read inputs of the storage device, the second output One lag detection unit is connected to. the second input of the decoder, the output of the binary address counter is connected to the control input of the storage device, the output of the digital-to-analog converter is connected to the fourth input of the comparison element and the input of the analog-to-digital converter is connected to the output of the predictor. · 1164661