SU1206751A1 - Digital self-adjusting system - Google Patents

Description

1206751

the higher frequencies are connected to the corresponding, the output of which is connected with the third ones appropriately with the first, second and third inputs of the first and second amplifier-inputs of the controlled divider of the frequency converters.

one

The invention relates to the field of automatic control systems, in particular to self-adjusting automatic control systems, and can be used in various automation devices in which a two-phase asynchronous motor is used as an executive and imposes high requirements on the static accuracy of the systems.

The purpose of the invention is to increase the static accuracy of the system.

The essence of the invention is that in a known system with a constant frequency of supply voltage of a two-phase asychronic engine (DBP), the possibility of changing its value is introduced with an unacceptable static error, usually accompanying a change in the operating conditions of the system. An algorithm is proposed for analyzing the values of the maximum and minimum static errors in the time interval corresponding to the period of natural oscillations of the system (and hence the static error. On its basis, the frequency of the DBP power is changed, aimed at preserving the permissible static error in the system.

The value of Z, QMKH | - Q ", is analyzed. q Q.qkc. Q / MHH - extreme maximum and minimum current static error values; iQml is the maximum absolute error value.

At Z O, the self-tuning circuit produces an increase in the frequency of the voltage of the DBP, at Z O, its reduction, while at Z O, the value of the frequency does not change. The frequency change is made by changing the coefficient (by adding or subtracting one from the unit on the reversible counter) to the nominal value, into which the frequency of the frequency generator of the increased frequency is divided into the controlled frequency divider. When the frequency of the DBP changes, the torque developed by the engine changes, thereby creating the possibility of a targeted change in the static error of the system. The process of frequency change stops when Z o is reached and resumes when Z is rejected.

from zero.

On. 1 is a functional diagram of a digital self-adjusting system; in fig. 2 and 3 - functional block diagrams for determining the maximum and minimum errors; in fig. 4 shows graphs of the possible types of static errors of the system over time; in fig. 5 - graphs of two-phase parameters change

induction motor when changing the frequency of the supply voltage.

The system comprises a first adder 1, a control circuit 2, an amplifier 3, a control winding 4, a two-phase asynchronous motor 5, a feedback sensor 6, a second amplifier 7, an excitation winding 8, a constant voltage source 9, a generator 10

increased frequency, the first, second and third units of determining module 11-13, the second and third adders 14 and 15, block 16 select the maximum value, the comparator 17, the inverter

18, first, second and third elements And 19-21, reversible counter 22, controlled frequency divider 23, first and second registers 24 and 25 of memory, fourth and fifth adders 26 and 27

a gate generator 28, a maximum detection unit 29 and a minimum detection unit 30.

The maximum definition block 29 contains the third and fourth registers.

memory 31 and 32, the second inverter 33, the sixth adder 34 and the fourth element And 35.

The maximum determining unit 30 contains the fifth and sixth registers 36 and 37 of memory, the third inverter 38, the seventh adder 39 and the fifth element I 40.

It is known from the theory of automatic control systems that a change in the frequency of the voltage of the DBP leads to a change in the general characteristic of the system due to a change in the transfer function of the engine. Shows graphs of the change in constant time.

Ta dad with transfer function in

to Wg (P)

-Ev

Ro t,)

where Kgg is the transmission coefficient of the engine and the moment M, c, developed by the engine at a constant amplitude and change in the frequency of the supply voltage

Having the ability to adjust the frequency of the DBP supply in a small limit (about 25% of the nominal value does not have a significant effect on the overheating and overload of the engine), as a result we get an additional power reserve and a means to influence the stability of the system, as well as constant change. engine time significantly affecting the transient time. Thus, we obtain an additional correction device that allows us to effectively influence the system in case of any changes in operating conditions.

The proposed system works as follows.

When a discrete input is received at the input of the input, the first adder calculates the error in (n) its test by the system, comparing the input signal value at the input (i) over the first input with the value of the signal from the feedback sensor 6 located on the shaft DBP 5, The result obtained by the control circuit 2 is corrected and converted into a pulse whose duration is proportional to the magnitude of the error. In the first amplifier 3, in accordance with the output signal of the control circuit 2 arriving at its first input, a pulse-width modulation of the carrier frequency pulses supplied from the controlled deligel 23 frequency to the third input of the first amplifier 3 is performed, and amplifying them

25

06751

before the voltage of the source 9 of the direct voltage supplied to the second input of the first amplifier 3. The voltage for the winding of the DBP 5 5 is formed at the output of the second amplifier 7, which carries out a phase shift 90 of carrier pulses to its third input from a controlled splitter for 23 hours, and amplifying them in amplitude to a voltage of the source 9 of a constant voltage supplied to the second input of the second amplifier 7.

So the main contour of the system is

 working off the input action, completing with some static error.

Static errors of type 41, 42, and 46 are considered valid. Rest

20 kinds of static errors to be fixed. The reasons for the occurrence of static errors of oscillatory nature (types 48, 49, 50) when the operating conditions of the system change may be the effect of non-linearity of backlash type and overestimation of the gain value of the open-loop system (for example, an increase in the voltage of the constant source 9). The reasons for the occurrence of static errors of a biased nature (types 42, 44, 45 and 47) when the operating conditions change can be a decrease in the transmission coefficient

35 of the closed system (for example, when the voltage of the source 9. Constant voltage decreases) and the increase in the dry friction moments (for example, thickening of the lubricant in the gearbox when

40 lower temperature).

It is proposed to eliminate the static errors that occur by changing the moment developed by DBP 5 when the frequency of its voltage is changed.

45 neither. Frequency adjustment is based on the analysis of the Z value.

 I Q "ax" jin I - I Q m 1 OF condition

the system achieves a permissible static error. In the case of the occurrence of static oscillatory errors (types 48, 49, and 50, Fig. 4), the frequency of the voltage of the DBP 5 increases, the time developed by it decreases (curve 52,

55 of FIG. 5), which leads to the elimination of fluctuations in error. In the event of the occurrence of a static error of a displaced chargister (, species 42, 44, 45 and 47,

FIG. A) the frequency decreases, the moment developed by DBP 5 increases, which makes it possible to eliminate this kind of error.

In order to ensure the operation of the frequency tuning circuit, only in the case of a jump input to the system, provide the enable input of the controlled frequency divider 23 (the first input), allowing it to operate when there is a logical unit signal on it.

Simultaneously with the testing of the main contour of the input discrete signal of 6 V, M, its first) and second (n) differences are calculated. The first difference is the addition of the current discrete action of the rp (n) arriving at the first input of the fourth adder 26, with its inverse value recorded in the first register 24 of the memory at the previous quantization time in (n-1) and post-quantizing to the second input of this adder Dp, the output of the fourth adder 26 of the value of the first difference in the direct code is added to the sum obtained

Bin-9in (-0 ,, (p-LIS signal of the first difference is fed to the first input of the fifth adder 27, which is similarly used to calculate the second difference) of the input. The current value of the signal of the first difference) is added with its inverse value at the previous quantization moment v9gy (nl), recorded in the second register of the 25th memory, and entering the second input of the second adder 27 and one

 0b, M 9 "Y - 9 x1 -) (The obtained values of the first and second differences of the input action are fed to the first and second inputs of the third element I 21, the output of which in the case of simultaneous zero equalization of the first and second differences of the input signal (in the case of the input jump) is the voltage of the logical unit that arrives at the first input of the controlled divider 23 of the frequency 4i allowing its operation,

In the time interval, approximately corresponding to the period of natural oscillations of the system and specified by the strobe pulse generator 28 (curve 51, fig. 4), Qfta and 9 min (maximum and minimum error values) are calculated by blocks for determining the maximum 29 and minimum 30 errors.

The error maximum determination unit 29 (FIG. 2) is operated as follows.

The current value of the static error in (n) arriving at its first input is recorded in the third memory register 31 and fed to the first input of the sixth adder 34, and in the next error discreteness period it is copied to the fourth memory register 32, the output of which is 0 ( nl) is inverted by the second inverter 33 and fed to the second input of the sixth adder 34, the latter compares the current value of the static error Q (n) and its value 8 (n-1) in the previous quantization period: in (n) -9 (n 1), for which the operation is performed in (n) + in (n-1) +1, qual The output of the sixth adder 34 is considered to be the sign (most significant) bit. A zero at the output is a sign that the value of a static error is not decreasing, and one is a sign of its destruction. The moment of changing the signal level from zero to one is a sign that the error has reached the maximum value of Qdcd, on the considered period the change in the static error. The output signal of the sixth adder 34 is fed to the second input of the fourth element 35, the first input of which is supplied with pulses from the generator 28 gating pulses (curve 51, fig 4). When the maximum error reaches the maximum value of the fourth signal, the output of the fourth element 35 is incoming On the second input of the fourth register 32 pam, it changes its level from zero to one. This prohibits further changing the contents of the fourth register of memory 32 in this period of the static error T, At the output of The maximum error determination value 29 is found by the blinks value found until the end of the static error oscillation period. At the end of period T, the gating pulse 28 of the gating pulse 28 arrives at the first input of the fourth element And 35, which is connected to the second input of the error maximum determination block 29. prohibition of overwriting from the third register 31 of the memory into the fourth 32, which removes from the second input of the fourth register 32 of the memory 32, this operation of finding the maximum static error is resumed L is already on the next periods de kolebayy static error.

The error minimum determination unit 30 (FIG. 3) is constructed and operates in a similar manner. Fifth memory register 36 records the current value of the static error 0 (n), and in the sixth memory register 3.7, the value of the static error in the previous quantization period (n -one). The seventh adder 39, to the first input of which the output signal of the sixth 37 is supplied, and to the second input — the output signal of the fifth memory register 36, inverted by the third inverter 38, is performed in (n-1) -b (n) 6 ( 1) + + e (n) +1. The moment of changing its output level from zero to one is a sign that the static error has reached a minimum value of 0, " at the period of its change. At the time the static error reaches the minimum value, the output signal of the fifth element AND AO arriving at the second input of the memory register 37 changes its level from zero to one. This prohibits a further change in the contents of the simple adder 37 in this period of fluctuation of the static error Tj ,, At the output of the minimum error determination block 30, the value O found remains until the end of the period of static error oscillation. At the end of the period T, the pulse from the gate pulse generator 28 through the fifth element I 40 passes to its output associated with the second input of the memory register 37, and removes from the latter the prohibition of rewriting the error value from the fifth register 36 of memory in the sixth 37 By this the operation of finding the minimum of an error is resumed already in the next period of its oscillation.

The values of the maximum and minimum errors found in this way are fed to the inputs of the second adder 14, which calculates the difference

"AKS ALIA I

206751.

The bmin module of which 1 is calculated by the third module 13 of the module definition and is fed to the first input of the third adder 15. The error values found from the extreme values are also fed to the inputs of the first 11 and second 12 modules of the module definition, where the modules of these values | max 1 and | 0 min 1 are calculated, then Q | to the inputs of the block 16 for selecting the maximum value that selects the maximum one. The output signal of the maximum value selection unit 16, which is the static error amplitude module J5 (0, n |, is fed to the second input of the third adder 15,

calculating on the interval T between the gating pulses the value of Z 19 max - - | e „|. The result is fed to the input of the comparator 17, analyzing this value.

At the first output of the comparator 17, a zero value is formed at Z 0, and a value equal to one at Z e O, the second output of the compass 17 is a significant bit of Z and equal to 1 at Z O and zero at Z O, The signal from the first output the comparator 17 is fed to the first inputs of the first 19 and second 20 elements And, to the second inputs of which are fed respectively inverted by the inverter 18 and direct signals from the second output of the comparator 17, and to the third,

These - the output signal of the generator 28 strobe pulses.

As a result of such a circuit with the case of Z O, the first 19 and second 20 elements AND, playing the role of gates, are closed and do not transmit a pulse from the generator 28 of gating pulses to the reversing inputs in the interval corresponding to the period of natural oscillations of the system.

counter 22. Thus, the contents of the counter do not change (before starting work, it records the nominal value of the division factor corresponding to the nominal

the power supply frequency of the DBP 5). When the first element I 19 opens, the pulse from the generator 28 of gate pulses passes to the input. The countdown of the reversible counter 22,

holding it decreases by one, thereby reducing the divider, which in the controlled frequency divider 13 divides the frequency of the generator

9

10 increased frequency, and the voltage of the power supply voltage DBP increases. At Z i O, the second element opens AND 20, the pulse from the gate pulse generator 28 passes to the input Direct through the reversible counter 22, its contents increase by one, thereby increasing the control divider frequency divider 23 frequency generator 10 increased frequency and decreases the frequency of the voltage of the DBP 5. Thus, the system produces a self-tuning of the frequency of the voltage of the DBP 5, aimed at providing a high static 0675110

precision of the input test under any changing conditions of operation.

It should be noted that when the input jump system is fed to the input, the self-tuning frequency of the DBP supply voltage frequency (VQg O, V QBX 0) turns on, the value of Z O being calculated, which causes a decrease in frequency and an increase in torque. An additional force is produced to the engine, significantly reducing the time of the transition process during the development of the input jump

15 by reducing the time constant of the engine (curve 52, fig. 5),

9tx1

in and)

34

32

9 (n-j

ffM L

3d

39

ff (n-l} 1

FIG.

Sh dv

53

0,

n

1, y

Fzg.5

Claims (1)

A DIGITAL SELF-SETTING SYSTEM containing a first adder, a control circuit and a first amplifier connected in series with the system input, the outputs of which are connected to a control winding of a two-phase asynchronous motor connected through a feedback sensor to the second input of the first adder, the second amplifier whose outputs are connected to the excitation winding two-phase asynchronous motor, a constant voltage source, the output of which is connected to the second inputs of amplifiers, and a generator of increased frequency, different due to the fact that, in order to increase the static accuracy of the system, three modules of module definition are introduced into it, the second and third adders, the maximum value selection block, comparator, inverter, three AND elements, reversible counter, controlled frequency divider, two memory registers, the fourth and the fifth adders, the generator of gating pulses, the block And determining the maximum and minimum errors, and the output of the first adder is connected to the first inputs of the maximum and minimum error determination blocks, whose outputs are connected to the first and second module definition blocks, connected outputs to the first and second inputs of the maximum value selection block, and the first inputs to the first and second inputs of the second adder, whose output is through the third definition block the module is connected to the first input of the third adder, the second input of which is connected to the output of the maximum value selection unit, and the output to the input of the comparator, the second output of which is connected to the second input of the second element And directly and the second input of the first element And through the inverter, and the first output - with the first inputs of the first and second elements And, the third inputs of the first and second elements And connected to the output of the strobe generator and the second inputs of the blocks determining the maximum and minimum errors, and outputs, respectively, with the inputs "Reverse counting" and "Direct counting" of a reversible counter, the first input of the first adder is connected with the first input of the fourth adder directly, and with the second input through the first memory register, output h of the fourth adder is connected directly to the first inputs of the third element I and the fifth adder, and through the second memory register to the second input of the fifth adder, the output of which is connected to the second input of the third element I, the outputs of the third element I, the reversible counter and the generator 1206751 higher frequencies are connected respectively to the first, second and third inputs of a controlled frequency divider, the output of which is connected to the third inputs of the first and second amplifying devices. one