SU1721834A1 - Clock rats phase-lock device - Google Patents

Abstract

The invention relates to telecommunications and can be used in discrete information transmission systems for clock synchronization. The aim of the invention is to improve noise immunity. The clock phase-locked loop contains a master oscillator 1, a phase difference estimation unit 2, an averaging unit 3, a switch 4, a first block for adding and excluding pulses 5, a first frequency divider 6, a phase zone former 7, a synchronization detector 8, a second addition block and excluding 9 pulses, second frequency divider 10, threshold unit 11, frequency discriminator 12, frequency discriminator start unit 13, frequency auto-tuning control signals 14 and frequency equalizer 15 mismatch. With the complete elimination of the phase and frequency mismatch received from the communication channel of the pulse signal and the output clock signal of the device, the detector 8 generates a signal that increases the degree of averaging information in the device. 3 hp f-ly, 5 ill.

Description

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The invention relates to the field of telecommunications and can be used in discrete information transmission systems for clock synchronization.

The aim of the invention is to improve noise immunity.

Figure 1 shows the structural electrical circuit of the phase locked loop device; FIGS. 2-5 show, respectively, the structural electrical circuits of the frequency discriminator, the driver of the control signals of the frequency auto-tuning, the frequency error corrector, and the frequency discriminator trigger unit.

The clock phase-locked loop contains a master oscillator 1, a phase error estimation unit 2, averaging unit 3, a switch 4, a first unit 5 for adding and eliminating pulses, a first frequency divider 6, a phase zone former 7, a synchronization detector 8, a second adding unit 9 and exclusion of pulses, the second frequency divider 10, the threshold unit 11, the frequency discriminator 12. the frequency discriminator triggering unit 13, the frequency-controlled control signals generator 14, the frequency converter corrector 15 oglasovanie.

The frequency discriminator 12 contains the RS-flip-flop 16, the first 1.7 and the second 18 frequency dividers, the modulator 19 modulo two, the selector of 20 fronts of the signal.

Shaper 14 of control signals of frequency auto-tuning includes switch 21, first 22 and second 23 elements ILYE, first 24 and second 25 pulse counters, frequency divider 26, RS-flip-flop 27, first and second elements AND-28 and 29 , element OR 30, D-flip-flop 31, element AND 32, selector 33 points of change of the signal's signs.

The corrector 15 frequency error contains the element OR 34, the reversible counter 35, the shift register 36, the comparator 37, the D-flip-flop 38, the second and first counters 39 and 40 pulses, the element 41, the first and second elements IL-AND 42 and 43, 44 front of the signal.

The frequency discriminator start block 13 contains a D-flip-flop 45, RS-flip-flops 46 and 47.

The device phase-locked loop operates as follows.

When a pulse of initial installation appears, the first block 5 of addition and elimination and the corrector 15 are given in

the initial state, and the operation of the second addition and elimination unit 9, the second divider 10 and the frequency discriminator 12 is prohibited.

In the absence of information on the information input of unit 2, the clock signal obtained by dividing the frequency of the master oscillator 1, comes from the output of the first divider 6 without phase correction.

0 Upon receipt of the information, the first loop of the phase-locked loop is activated, the operation of which is aimed at eliminating the initial phase and frequency mismatch of the clock signal

5 at the output of the first divider 6 and the received pulse (information signal).

In this case, depending on the mismatch sign, in block 2, a sequence of pulses corresponding to the significant moments of the information signal is generated and output to its corresponding outputs. Correction pulses from the outputs of block 2 are averaged in the averaging block 5 and further fed through the switch 4 to the first block 5 of addition and elimination. When providing clock synchronization, when the output clock signal and the information signal are phased, and their frequency divergence is compensated, the detector 8 is triggered, the output signal of which triggers through the start block 13 of the frequency discriminator 12 and the second divider 10.

In this, the following sequence of operation of the nodes is carried out. When a start pulse arrives at the enable input of the start block 13, a signal is generated at one of its outputs

0 allowing the second divider 18 of the frequency discriminator 12 to work. After a time equal to the period of the signal at the output of the second divider 18, a signal is set at the corresponding output of the launcher, phasing the first 17 and second 10 dividers from the output of the second divider 18.

In this case, due to the work of the first phase auto-tuning, the period of clock

0 of the signal at the output of the first divider 6 is equal to the duration of the elementary pulse of the information signal with an accuracy of one correction step, and the frequency of the output clock of the second divider 10 is determined only by the natural frequency of the driving oscillator 1. Due to the difference in the frequencies of the transmitting and receiving sides, the phase mismatch of the specified output signals of the first and second dividers 6 and 10. Between the output signals of the first 17 and second 18 dividers, a phase mismatch also forms, which increases are each tact and whose sign is defined by the frequency discriminator 12 and the generator 14 is essentially independent of interference in the communication channel. In this case, a pulse signal and a lead / lag signal to a corrector 15 are received from the imaging unit 14, in which the pulses of the specified pulse signal are directly or inversely calculated.

Depending on the Advance or Delay mode, a clock sequence appears at one of the outputs of equalizer 15, whose frequency is proportional to the number of 14 pulses from the generator, each of which changes the frequency of the output clock sequence of corrector 15 by one increment in the direction of its increase. This clock sequence enters the second addition and subtraction block 9, closes the feedback on the second loop of auto-tuning, and first blocks 5 of the addition and elimination, improving the operating conditions of the first loop of phase-locked loops.

The operation of the frequency discriminator 12 and the former 14 is performed cyclically, when it is periodically set to the initial state and restarted under conditions of synchronization confirmed by the detector 8. At the same time, a signal from the frequency discriminator 12 arrives at the start block 13, indicating the end of its operation cycle. The start-up unit 13 generates signals that prohibit the operation of the frequency discriminator 12, the driver 14 and the second divider 10. If synchronization is confirmed by the detector 8, the indicated nodes restart and the first and second dividers 17 and 18 are phased. The signal at the output of the second divider 10 determined by the difference (sum) of the frequency of the master oscillator 1 and the frequency of the pulses at the output of the equalizer 15. The described data acquisition process continues until, for a given cycle time, the frequency The discriminator 12 makes it difficult to reliably determine the sign of the phase mismatch of the signals at the outputs of the first and second dividers 6 and 10 and the effect of interference in the communication channel, i.e. in the coarse mode, there is no assured determination of the phase mismatch sign.

At the same time, the value of the signal read into the shaper 14c of the frequency discriminator 12 is not determined and its constant change in time occurs. Here, a pulse signal is received from the imaging unit 14, the number of pulses of which is detected by a threshold unit 11, the state of which will change if the number of said pulses exceeds a predetermined threshold value. In this case, the transition to the Exactly operation mode occurs, in which the exact determination of the frequency difference between the oscillators and its compensation using additional resources of the averaging unit 3 is dynamically performed by connecting the first unit 5

addition and exclusion to the first and second additional outputs of the averaging unit 3. At the same time, the cycle time of the frequency discriminator 12 and the degree of accuracy about the sign of the frequency error of the clock signals of the first and second dividers 6 and 10 increase.

Claims (4)

1. A phase-locked loop clock device comprising a series-connected master oscillator, a phase difference estimation unit, an averaging unit, a switch, the first unit addition and exclusion of pulses, the first frequency divider, the phase zone former, the synchronism detector, the clock input of which is combined with the clock input of the first addition and exclusion unit and connected to the output of the master oscillator, the second addition and pulse exclusion unit and the second frequency divider, input additions and exclusions The second addition and exclusion unit is connected respectively to the auxiliary input and the exclusion input of the first addition and exclusion unit, the output of the first frequency divider is connected to the input of the reference clock signal of the phase error estimator, the clock input of the second addition and exclusion unit is connected to the output of the master oscillator, and the installation input of the first unit for adding and excluding pulses to the setting input of the second unit for adding and excluding pulses, The information input of the phase error estimator, the setup input of the additional pulse addition and exclusion unit, and the output of the first frequency divider are, respectively, the information input controlling the input and output of the device, which is different from increased noise immunity; a frequency discriminator startup block, a frequency discriminator, a frequency self-tuning control signal generator and a threshold block, and a frequency error corrector are inputted; the first and second auxiliary outputs of the averaging block are connected to the first and second additional information inputs of the switch , the control input of which is combined with the input of the Coarse / accurately signal generator of the control signals of frequency auto-tuning and connected to the output of the threshold unit, the information input of which is combined with the installation input of the frequency-controlled frequency control control signal generator and connected to the cycle output of the frequency discriminator trigger unit, the input of which the clock signal of the synchronization detector and the first output of the clock signal of the frequency discriminator, the second output of which is connected to the gate of the gate signal the control signal generator of the frequency auto-tuning, the output of the first frequency divider is connected to the inputs of the reference clock oscillation of the frequency discriminator and the frequency error corrector, the first and second outputs of which are connected respectively to the input of the addition and the exclusion input of the second addition and pulse exclusion unit, the output of the master oscillator is connected to clock inputs of the frequency discriminator startup unit, the frequency discriminator and the frequency error corrector, the left and second control inputs of which are connected respectively to the signal output Advance / lag and signal output Increase / decrease the frequency of the frequency control loader control signal output, the output of the blocking signal and the sign input of the error signal of the frequency difference of the frequency discriminator and the output of the sign signal of the frequency mismatch of the frequency discriminator auxiliary input of the reference clock signal combined with the input of the reference clock signal shaper steering lock loop frequency signals and connected to the output of the second frequency divider, a control input of which is connected to the output signal synchronous start, the first and second outputs of the averaging unit are connected respectively to the first and second information inputs of the synchronization detector, and the installation inputs of the frequency discriminator triggering unit and the frequency error corrector are connected to the installation input of the second addition and removal unit. 0 2. The device according to claim 1, from l and to the other hand, with the fact that the frequency discriminator contains in series the first frequency divider and the modulo two, in series connected the second 5 frequency divider, signal edge selector and RS trigger, the first output of the first frequency divider is connected to the second input of the edge selector, the first input of which is connected to the second input of modulo two, the clock input and the setting input of the first frequency divider, clock input and The setup input of the second frequency divider, the clock input of the edge selector, the second, third and even fifth outputs of the first frequency divider, the output of the modulo two adder and the output of the second frequency divider are respectively complemented nym input reference clock signal input sinhroniziruyu0 incoming signal, the reference clock input, enable input, a clock input, output strobe signal Sign frequency mismatch, the output interval signal analysis Roughly, vy5 progress analysis interval signal mode Similarly, the output clock signal. 3. The device according to claim 1, wherein the equalizer of the frequency mismatch contains a series-connected reversible counter, shift register, comparator, OR element, the leading edge of the signal, the first pulse counter, the second pulse counter, the outputs of which are connected to the corresponding inputs of the comparator, the D-flip-flop and the first OR-NOT element in series, and the second OR-NOT element and the AND element, whose inputs are connected to the outputs of the shift register, the clock input of which is connected to t to the D input of the D-flip-flop, the control input of the shift register is combined with the first input of the second element OR NOT and sub5 keys to the output of the D-trigger, the D input of which is connected to the output of the higher bit of the reversible counter, the setting input of the second pulse counter and the second inputs the first and second elements are OR NOT connected to the output of the front allocator of the signal edges, the clock input and the setup input of which are connected respectively to the contact input of the pulse counter and the control input of the reversible counter, and the output of the AND element are connected to another input of the OR element, the clock input of the first pulse counter, the clock input of the D-trigger, the direction input signal accounts, clock input and installation input of the reverse counter and the output of the second and first elements OR NOT; are, respectively, a clock input, a reference clock input, a first and second control inputs, a setup input, and the first and second outputs of a frequency error equalizer. 4. Device. By. Claim 1, P.T.L.ch.W .: so that the driver of the frequency-controlled control signals Contains a series connected moment extractor of a change in the sign of the signal / first element OR-HB ,. the first pulse counter, the RS trigger and the switch,; are connected in series the second element OR-NOT, the second pulse counter, the first and second AND-NOT elements, Df rigger and the AND element, and the tayut frequency divider and the OR element, the first input of which is combined with the S-input of the trigger and is connected to the output of the second; pulse counter, the setup input of which is connected to the setup input; The first pulse counter and the second input element 1 / H, the output of the first pulse counter is connected to the second inputs of the first OR element, the output of which is connected to another input of the second NAND element, a clock input, a clock input and the first and The second outputs of the signal divider are changed respectively to the clock inputs of the D-flip-flop frequency divider, the inverse input of the second element OR-NOT and the setting input of the frequency divider, the second input of the first element OR is NOT connected to the second input of the second element OR-NOT, and the outputs frequency dividers and element And the information input of the selector of the moments of change of the signal's sign is connected respectively to the second, third and fourth information inputs of the switch, and the clock input, synchronization input and information input of the moment selector of the change of the signal's sign, the fifth and sixth information inputs and the control input of the switch, the second input of the first element OR-NOT, the installation input of the first counter, pulses, the second output of the moment selector; the sign of the signal and the first, second and third outputs of the switch are respectively the input of the reference a clock signal, a strobe signal input, a sign signal of the frequency error signal, an input of the interval signal. Rough analysis, an input of the signal of the analysis interval. Precisely, a signal input Coarsely / accurately, signal input magnitude frequency mismatch signal input and output Repeating the sign of the frequency error, output signal; Advance / lag, signal output Increase / decrease in the frequency of the output signal of the blocker of the driver of the control signals of the frequency self-tuning. I FIG. five