SU1711201A1 - Image logical processing unit - Google Patents

Abstract

The invention relates to automation and computer technology and can be used to implement matrix optical processors. The purpose of the invention is to increase the speed of the device. The device contains matrices of memory cells and matrixes of logic cells, as well as a control unit, an illuminator and an optoelectronic shutter. A positive effect is achieved by reducing the number of processing cycles, as well as the use of Bispin-photodetectors as part of the cells. 2 h, para. f-ly. 4 il.

Description

The invention relates to automation and computing and can be used to implement matrix processes.

The purpose of the invention is to increase the speed of the device ..

Figure 1 presents the block diagram of the device; 2 shows a control unit; on fig.Z - generator circuit; figure 4 - scheme of the one-shot.

The device contains (n + 1) matrices of memory cells 1, n matrices of logic cells 2, an optoelectronic shutter 3, an illuminator 4 and a control unit 5. The cells consist of bis-photodetectors 6, photodiodes 7, LEDs 8. In addition, the capacitor cells are part of the logical cells. The collimator 10, the device start input 11, the first and second outputs 12 and 13 of the block are also shown in FIG. management

The control unit b (figure 2) contains a generator 14, (n + 1) -disable counter 15, the outputs of the bits of which form the first group of inputs of the switch 16, the second group of inputs of which are connected to the outputs

the corresponding keys 17i - 17Р (). The generator 14 output 18 is connected to the counting input of the counter 15.

The generator (fig.Z) contains the element OR 19, one-shot 20i-20p, the element OR 21.

The single vibration comprises (FIG. 4) a resistor 22, a transistor 23, a bispin device 24, a capacitor 25, a resistor 26, an LED 27, a resistor 28, an RS flip-flop 29.

The device works as follows.

To calculate the value of a given (arbitrary) logical function of the n information operands of the picture type, it is necessary to compile 2P minmeters of input operands, which are products of combinations of direct and inverse input operands. Then each logical function will be assigned a set of enabling signals of a third or other minmeter. included in the formation of the named logical function, i.e.

Ј f (xixn) 2 / TjAj,

J 1

(L

with

ho

about

where Aj is 1 if Tj is included in the logical sum, and AJ 0 is otherwise.

Thus, the essence of the computational process is the sequential formation in time of the values of the current minterms and, in accordance with one or another logical function, their resolution (inclusion) or prohibition. Such formation in the device is based on the use of the properties of bispin photodetectors, which convert optical signals arriving at their optical input, into the duration of a certain time interval of the delay. If an optical signal is fed from the input x2 to the optical input of the corresponding bispin-photodetector 6, then the output of the corresponding led 8 appears sequentially separated by a certain time interval Ti pulses xi xi to Nihi where Ni is the value of the part of the arbitrary minterm formed by the previous information operands . Thus, in the device, the values of all current minters are sequentially arranged in time, with the corresponding control signal from the first output 12 of the control block. 5 allowing the corresponding generated minmeter to pass through the optoelectronic shutter 3. The last matrix of memory cells 1p + 1 provides an accumulation of allowed values of the minterms and the formation of the final result of the calculations.

The delay time Tj depends on the intensity of the input operands, the voltage of the power supply and the capacitors, and the capacitors 9. With constant power and consideration of the binary operands, the time delay is proportional to the corresponding applied capacitance. As a result, an appropriate selection of the capacitance in each of the logical cells, and hence the delay time of the formation of a sequence of minter values, ensures the formation of all possible 22n values of the corresponding logical functions.

On the other hand, at the appropriate time points, the corresponding permitting signal generated by the control unit 5 must be supplied to the input of the optoelectronic shutter 3.

When a signal is applied to the launch input 11 of the device, electrical signals are generated at the output 18 of the generator 14 sequentially in time. The delay of the signals is provided by each of the single-shot 20i-20p, and the delay time is proportional to the resistance selected on the variable resistor 28. Consequently, single signals will be received at the counting input of the counter 15 at time intervals η.

The key states are selected depending on the value of the calculated function, i.e. the signal is generated at the outputs of those keys 17i-17p, the values of the corresponding terms of which should be included in the logical sum in the final formation of the result. At the initial moment of time, the counter value is one, therefore, depending on the state of the first key 17i, 1 or O is formed at output 12. Then, after time n, the counter value is two, therefore, depending on the state of the second key 172, output 12 1 or O is formed. And so on. until the counter value becomes 2, when the last control signal is generated.

Thus, the generation of control signals is realized synchronously in time with the formation of the corresponding current values of the minters.

The device provides the implementation of the entire spectrum of logical functions of picture operands at high speed, due to the small number of cycles and high speed Bispin-photodetectors. At the same time, due to the simultaneous supply to the xi inputs of picture operands, there is no need to use additional memory blocks to store operands.

Claims (3)

Claim 1. A device for logical image processing comprising a control unit, a memory unit made in the form of a first matrix of memory cells, the first and second inputs of which are connected respectively to a positive voltage bus and a zero potential bus, and a logic function generating unit made in the form of the first matrix of logic cells, the first and second inputs of which are connected respectively to the positive voltage bus and the zero potential bus, the first optical inputs of the logic cells of the first The matrices are associated with the optical outputs of the respective memory cells of the first matrix, characterized in that, in order to increase the speed of the device, additional memory cell matrices are added to it, where n is the number of processed images, the first and second inputs of which are connected respectively to the bus a positive voltage .and a zero-potential bus, and n-1 matrixes of logic cells, the first and second inputs of which are connected respectively to the positive voltage bus and a zero potential bus, as well as an optoelec a tronic shutter and an illuminator connected, respectively, to the first and second outputs of the control unit, whose input is the device start input, the optical outputs of the memory cells of the 1st (1-2, ..., n) matrix are connected With the first optical inputs, respectively, of the logic cells of the 1st matrix, the optical outputs of the logic cells of the jth 0 1n-1) matrices are associated with the first optical inputs of the corresponding memory cells of the 0 + 1) -th matrix and the second optical inputs of the corresponding memory cells of the j-matrix, the optical outputs of the logical cells of the n-th matrix are connected with the second optical inputs of the memory cells The n-th matrix and via the photoelectric shutter — with the first optical inputs of the memory cells (n + 1) -th matrix, the optical outputs of which form the information optical output of the device; the illuminator is optically connected to the first optical inputs of the memory cells first and (n + 1) -th matrices, in orye optical inputs of the first logic cells -ch1 minutes matrix form, respectively, a first n-th optical information input device. 2. Pop-1 device, characterized in that each cell / memory contains a bispin photodetector, a photodiode and a light emitting diode, the first electrode of a bispin photodetector is connected to the first input of the second and third electrodes of the diode and the photodiode cathode, the photodiode anode and the LED cathode are connected to the second cell input, the optical output of the LED is connected to the optical input of the bispin photodetector, the optical inputs of the photodiode and the photopin diode are respectively the first and second optical inputs eyki and optical output of the LED - its optical output. 3. The device according to claim 1, wherein the logical cell each contains a bispin photodetector, a photodiode, a light emitting diode and a capacitor, the first electrode of the bispin photodetector is connected to the first input of the cell, the second and the third electrodes are connected respectively to the anode of the LED and to the cathode of the photodiode interconnected via a capacitor, the anode of the photodiode and the cathode of the LED are connected to the second input of the cell, the optical inputs of the photodiode and the bispin photo. receiver are respectively the first and second optical inputs of the cell, and The output of the LED is its optical output. Fy Jl Schi 1 SchigZ Q + f Schigl