SU1668984A1 - Device for logical image processing - Google Patents

Abstract

The invention relates to automation and computing and is intended for image processing systems using cellular logic techniques. The aim of the invention is to increase the speed and simplify the device. The device contains blocks of optical delay elements, an optoelectronic shutter, a matrix of storage elements. Each block of optical delay elements consists of an array of storage elements and an array of pulse shapers, each of which contains bispin photodetectors, light emitters, and photodetectors. Thanks to the use of new elements - bispin photodetectors and new connections, the device operation speed and simplicity of its realization are high. 3 hp ff, 4 ill.

Description

The invention relates to automation and computer technology and can be used in various optoelectronic parallel image processing circuits in the construction of matrix processors, for calculating the logical functions of images using cellular logic methods.

The purpose of the invention is to simplify the device, due to the use of bis-bin photodetectors as base cells of the device, and the associated increase in the speed of the device.

FIG. 1 shows a block diagram of the device: FIG. 2 illustrates the implementation of the cells of the optical delay lines of the device; in fig. 3 - timing diagrams of the device: in Fig. 4 - the dependence of the delay time on the intensity of the information operands.

The device contains n consecutive blocks of 1 g-1p optical

the delay lines controlling input 2 of each of which is the corresponding information input (l-1-n) of the device, the optical start input of each block 1 is connected to the optical output 3 of the previous block, the start input of the first block is the optical start input 4 of the device. Each block 1 consists of a matrix of 5 storage elements, RS-flip-flops, a matrix of 6 pulse shapers, and the launch launch of block 1 of optical delay lines is the R-input of the matrix of flip-flops, the optical output of which, together with the control input of block 1 of optical delay lines 8, form The first and second optical inputs of the array of pulse formers, the optical output of which is the optical output of the array of optical delay lines and forms the S input of the trigger matrix, the optical output of the last unit 1 is connected to the optical ichically

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Os

00 S 00

s

an optoelectronic gate 7, with a control input 8, the optical output of which forms the S input of the matrix 5 RS flip-flops of the device, the RS input of which is connected to the start input of the device, and the optical output connected to the optical output 9 of the device.

The device contains in each of blocks 1 (FIG. 2) n information optical inputs 2i-2n, optical start input 4, n consecutive operating elements 10ijK (,,), each of which contains the first 11 and the second 12 Bispin-photodetectors, the first 13 and second 14 photodiodes, the first 15 and second 16 LEDs, a resistor 17 and a capacitor 18. The power supply terminals of the bispan photo receivers are connected together and connected to the power supply bus of the device, the additional leads of the first 11 and second 12 bispec photo detectors are connected to the first leads accordingly n The first 13 and second 14 photodiodes, the locking pins of the first 11 and second 12 bispin photodetectors, are connected to the anodes of the first 15 and through the resistor 17 of the second 16 LEDs, the additional and locking leads of the second 12 bispin photodetector are connected to the capacitors 18, the optical input of the second Bispin photodetector 12 is the corresponding information optical input 2 of the device, the optical output of the first LED 15 is connected to the optical input of the second photodiode 14, the optical output of the second LED 16 is connected to the optical The input of the first bispan photodetector 11, whose optical input is also connected to the optical output of the first LED 15, and forms the optical output 3 of the array and the cell, connected to the optical trigger input of the next cell, is the trigger signal of the first cell the optical trigger input 4, the optical output 3 of the last cell forms the optical input of the optoelectronic shutter 7, the optical output is connected to the optical input of the corresponding cell of the RS 5 flip-flop matrix 5, each of which has holds a bispin photodetector 11, the power output of which is connected to the device power bus, the locking output is connected to the anode of the LED 15, the optical output of which forms the optical output 9 of the device, the additional output of the bispin photodetector 11 is connected to the first output of the photodiode 13 whose optical input is the corresponding start signal 4 of the first cell, all the second leads of the LEDs are connected to the zero potential bus, the control input 8 of the gate 7 forms the control input of the device.

FIG. 3 shows a hyperbolic

dependence of the intensity of the input operands A | from the delay time r, in Fig. 36, a table shows the total intensity from the three input operands and the corresponding delay time.

0 The device operates as follows.

To form a logical function

f (AiAn) should form 2 terms

images, each of which consists

5 of the product of the combination of direct Am or inverse AT images. The essence of the operation of this device is that a (n + 1) group of terms is formed that are indistinguishable from each other. This formation is performed according to the rule: in the first group, only the direct images; Here, the first group consists of one term, in the second group one inverse and (n-1) direct images. There will be such terms

5 items. In the third group, 2 inverse and (p-2) direct images and the like are formed. In general, the m-group contains terms, and there will be (n + 1) such groups, i.e. (n + 1). Then each logical function is built

0 according to the rule: to give or not to give permission for the accumulation of the corresponding group of terms by applying the appropriate signal to the control input 18 of the device. The formation of each of the groups takes place 5 consequently in time and, by opening or closing the shutter 7 of the device, the permission or prohibition of one or another group of terms occurs. If there are 2 such groups (n + 1), then there will be 2 different logical functions (in total, as

0 is known using n operands can form 22n + 1 functions, since the number of different terms is 2).

Since the optical signal Ak is binary, the threshold value of zero

Level 5 is chosen such that the bispan photodetector 12 of each cell is in the conducting state, i.e. the zero level corresponds to a gray background light. When exhibiting information

0 operands Ak at the inputs 1 to the device, the optical transitions OK of the connection of the first LED 15 and the second photodiode 14 are in a single state, since At the start-up input 4 of the device, the optical signal is missing, and the optical signal from the output of the second LED 16 is prepared by the first bispin photodetector 11. The resulting pulse at output 3, which is the optical input of the first photodiode 13 of the next cell, has no effect

renders, since the first bispin photodetector 11 of the same subsequent cell has not yet been prepared. Thus, the filing of information operands Ak only prepares the appropriate cells for operation. And now the first photodiode 13 becomes illuminated by the signal from the optical launch input 4. Therefore, the first LED 15 is quenched, the second photodiode 14 is not illuminated. If there is 1 on the optical AI input, then a single pulse also appears on the optical output 3 of the second LED 16 proportional to the intensity of the optical input signal AL. But if there is no signal at the optical input AI, then at optical output 3 a signal is delayed by the capacitor 18 of the first cell, and the delay time is proportional to tional capacity of the condenser. Thus, the trigger signal causes the first cell signal of the direct and then delayed and delayed ingress of the optical signal with respect to the input signal from the AL operand to appear at the optical output 3 relative to the output signal of the first cell and is the trigger signal for the second signal cells of the first bispin photodetector 11, which has already been prepared. The work of the second cell is similar. At the same time, at the output 3 of the second cell with time division 2i, groups of signals are sequentially formed: first, AiA2, then AiA2 + AiA2, and AiA2. The first bispin photodetector 11, the photodiode 13 and the LED 15 form an RS flip-flop 5, where the R input forms the optical input of the photodiode 13 with the optical output being the output of the LED 15.

Claims (4)

Thus, at the output 3 of the last cell, a (n + 1) group of terms is formed, according to which one or another logical function is formed sequentially in time. The accumulation of term group values is carried out by the cells of the last matrix, each group is fed to accumulation or not, depending on the control signal at the control input 8 of the optoelectronic gate 7. The last cell is pre-cleared by the device 4 start signal. The accumulation occurs due to the optical feedback of the LED 15 with the bispan photodetector 11. The value of the logic function is formed at the optical output 9 of the device. Claim 1. A device for logical image processing, containing its sequentially arranged blocks of optical delay elements, the control inputs of which are information inputs of the device, the trigger input of each block of optical delay elements is connected to the output of the previous block of optical delay elements, the trigger input of the first optical block the delay elements is the device launch input, which is characterized by the fact that, in order to increase the speed and simplify the device, it contains it is an optoelectronic gate and a matrix of storage elements, the output of each block of optical delay elements is optically connected to its information input, the output of the last block of optical delay elements is optically connected through an photoelectric gate with a reset input of the matrix of storage cells, copiers, the information input of which is optically connected with the trigger input of the first block of optical delay elements, and the output of the device, the control input of the photoelectric shutter is the control input of the device. 2. The device according to claim 1, that is, so that each block of optical delay elements contains a matrix of storage elements and a matrix pulse formers, whose information inputs are the control input of the block, whose information input is the integrated information inputs of the matrix elements, the reset inputs of which are the block start input, the outputs of the array of storage elements are optically coupled to the control inputs of the matrix of pulse shapers, the outputs of which are the output of the block. 3. The device according to claims 1 and 2, characterized by the fact that the matrix of storage elements consists of bispin photodetectors, light emitters and photoreceivers, the electrical inputs of which are connected to the first electrical inputs of the bis-photodetectors, the second electrical inputs of which are connected the electrical outputs of the light emitters, whose optical outputs are optically coupled to the optical inputs of the bispan photo receivers, and are outputs of the array of storage elements, information inputs and inputs which dumpings are respectively the optical inputs of the bispan photodetectors and photodetectors. 4. Pop-1 device, characterized by the fact that the matrix of pulse shapers consists of bispin photodetectors, light emitters, photodetectors and RS-flip-flops, whose inputs are connected to the electrical inputs of the bis-photodetectors, outputs to the electrical input and 5 the outputs of the light emitters are the output of the photodetectors and the light emitting outputs of the array. (respectively, the information and control inputs of the array are, respectively, the optical inputs of the bispin photodetectors and photodetectors, and Fi..1 Fi.g "about 7, J  Q P bkhz f-0 YCh-O Qt breathing 2nd h bhw | ) J eight (w ;; P Bkb (rum A4MLg) U) j L L year