SU1465913A1 - Optronic shift register - Google Patents

Abstract

The invention relates to computational and information-measuring technology and can be used in devices for shifting and visualizing images. The aim of the invention is to expand the scope of the register due to the possibility of performing a reverse shift. To achieve this goal, in each register register, consisting of three memory elements 2, a fourth, memory element is introduced. Each memory element consists of a series-connected photo-transistor 3, a resistor 4, and an LED 5. The LEDs of each memory element are optically coupled to the photo-thyristors of the neighboring memory elements. Information is shifted using signals from four clock inputs 6–8. To change the direction of the shift, the clock signal sequence is changed. 2 Il. with y

Description

0l / & f

The invention relates to computational and information-measuring technology and can be used in devices for shifting and visualizing images.

The aim of the invention is to expand the field of application of the register due to the possibility of performing a reverse shift.

Fig, 1 shows the register; in FIG. 2, pr1: the use of a register in an image shifter.

The register (FIG. 1) contains n bits 15 each of which consists of four memory elements 2 (EP) formed by series-connected photothyristor (FT) 3, a 4-l resistor by light-emitting diode (LED) 5., FIG. 1 shows also four clock inputs 6–9 registers, the first 10 and second 11 optical information inputs and the first 12 and second 13 optical information outputs of the register.

The register works as follows

If at all clock inputs 6–9 of the register is zero potential, then the FT 3 of all ESs are j3 nonconductive, and the corresponding LEDs 5 do not radiate. This corresponds to the zero state of the register bits.

When voltage is applied to the first clock input 6, the first EPs of each of the bits of the register are transferred to the conducting (excited, single) state only if the corresponding LEDs 5 of the fourth EPs of the previous bits were in the excited state. The state of the first transducer of the first discharge is determined by the presence of an optical signal at the first information input 10 "LEDs .5 of the first transducers of each of the discharges in the excited state, prepare the operation of the FT 3 of the second transducers of these discharges and fourth EPs of the pre-diffusion ( their discharges

If the voltage is now supplied to the second clock input 7, simultaneously removed at the first clock input 6, then the states of the second ES in each of the bits will be correspondingly the state of the first ES. This will prepare the operation of the third and first ES of these bits. The duration of each of the clock signals

0

five

0

five

0

five

0

five

0

five

not limited from above. In this case, static information storage is performed.

If you apply voltage again. to the first clock input 6 (in the absence of the remaining clock inputs 7-9), the information will again be overwritten in the first ES of each bit. Thus, it is possible to carry out the process of dynamically storing information sequentially on the first, then on the second EP of each of the bits.

If it is required to shift the optical information to the right, then the voltage should be applied to the third clock input of the 8th register, and then to the second. At the same time, the information will be rewritten into the third ES of each of the bits. When voltage is applied to the fourth clock input 9 (and removed from the third), the information will be overwritten by the fourth EA in each bit. This will complete the information shift period to the left by one bit. Thus, to shift the information to the right, clock signals should be given in the sequence 6.7, .8, 9, b, etc.

To shift information to the left, clock signals should be n, in reverse order — 9, 8, .7, 6, 9, etc. In this case, the input information is fed to input 11, .. and the output information is removed from output 13.

FIG. 2 shows the scheme of using the register for parallel shifting of arrays of information (binary images). The set of register structures with common clock | Tric inputs 6-9 is presented in the form of a matrix of M N N registers. The combination of the first 10 and second 11 information inputs of the registers forms the first 14 and second 15, respectively, the input optical apertures of the device, and the set of the first 12 and second 13 information outputs of the registers - the first 16 and second 17, respectively, the output optical apertures of the device. The operation of each of the matrix registers is carried out in parallel by combining the corresponding clock inputs per gist. In such a device, you can store (statically and dynamically) and move whole to the right or left

arrays of optical information of dimension.

Claims (1)

Invention Formula  An optoelectronic shift register containing three memory elements in each bit, each of which consists of a series-connected photo thyristor, a resistor and an LED, and in each bit of the register optical outputs of the first and second memory elements are connected to the optical inputs of the photo thyristors the second and third memory elements, the optical input of the photothyristor of the first memory element of the first bit is -: - with the first information input of the register, characterized in that, in order to expand In order to use a reverse shift, a fourth memory element is inserted in each register bit, consisting of series: connected photothyristor, resistor and LED, and each time the optical output of the third memory element is connected to the optical input the photothyristor of the fourth memory element, and the optical output of the LED of the fourth memory element each. The second bit of the register, except the last one, is connected to the optical input. ten 15 20 25 thirty 4659134 the photothyristor of the first memory element of the subsequent register bit, the optical output of the LED of the fourth memory element of the last register bit is the first information output of the register; in each register bit the optical output of the LED of each memory element, except the first, is connected to the optical input of the photothyristor of the previous one memory element, the optical output of the LED of the first memory element of each bit, except the first, is connected to the optical input of the photothyristor of the fourth memory element previous its register bit, the optical input of the photothyristor of the fourth memory element of the last bit of the register and the optical output of the LED of the first memory element of the first register bit are respectively the information input and output of the register, the anode of the photothyristor of the first. and the cathode of the second memory element LED, the cathode the LEDs of the first and the anode of the photothyristor of the second memory elements, the anode of the photothyristor of the third and the cathode of the LED of the fourth memory elements and the cathode of the third LED and the anode of the photothyristor of the fourth of memory elements each bit registers are respectively the first, second, third and fourth register clock inputs. 35