SU1709351A1 - Device for localizing failed units and members - Google Patents

Abstract

The invention relates to computing and can be used in specialized computer systems and information-measuring complexes. The purpose of the invention is to expand the field of application of the device by simultaneously controlling dissimilar typical units of computer technology. The device contains two memory blocks 2 and 3 of the fault table, the evaluation register 5. the object parameter register 10, the evaluation unit 1 of the health code, the first block of elements 11 AND, the result register 12, the display unit 13. Additionally, two counters 1 and 21 are entered into the device , two blocks 4 and 8 elements OR. the second block 6 And elements and block 15 of the control of the result with the corresponding / connections. 3 hp f-ly, 14 p., Utabl. (Dut.J-CHOYu00 CJI

Description

The invention relates to the field of computing and digital automation and can be used in specialized computing systems, control complexes and information-measuring devices.

A device for searching faulty blocks and elements is known, which contains registers of object parameters and parameters, a fault table, a logic matrix for comparing binary parameter codes from monitored blocks and binary fault table codes, a diagram for selecting the number of faulty blocks, and a display unit.

However, the increase in speed is achieved in a known device due to too high hardware costs, which impede the practical implementation of the device, since its complexity is more than five times more than the object itself being monitored.

The closest in technical essence and the achieved result of the present invention is a device for searching faulty blocks and elements, containing a register of columns and a register of object parameters, the outputs of which are connected to a serial circuit in a binder of a comparison block, an evaluation unit, a evaluation register, a unit selection unit, an encoder , the first and second permanent memory (ROM), the register of the output block of AND-NOT circuits, the block of circuits L, the result register and the display block, which are controlled by the block an independent control input, the outputs of which are connected to all registers of the ROM units and the selecting unit.

The disadvantage of this device is its structural complexity, expressed in the presence of an encoder, a comparison unit, several registers and a complex unit selection unit, as well as its narrow functionality limited to implementing only the direct search functions for faulty units and elements and displaying the result for analysis by the operator . In addition, this device cannot be used (without changing its structure or inserting external blocks) in control and microprocessor complexes with an automatic decision mode, since it does not contain circuits for outputting results to such complexes and has no means of verifying the validity of the control. i.e. whether the search device itself was working properly during its operation: a device cannot be used to check elements of computing technology

BIS ROM, PLA, descrambler and others, which are the basis of the construction of computing and control devices.

The aim of the invention is to expand the field of application of the device by simultaneously controlling dissimilar typical units of computer technology.

The goal is achieved by the fact that in the device for searching for faulty blocks and

0 elements containing two memory blocks of the fault table, a health code evaluation unit, an object parameter register, the first AND block, a result register, a control unit and a display unit, an input

5 of which is connected to the output of the direct result register code, the information input of which is associated with the output of the first block of elements AND whose input groups are connected to the output group of the code evaluation block

According to the invention, according to the invention, two counters are additionally introduced, two blocks of OR elements, the second block of elements I and a control unit of the result, the setting inputs whose information and indication outputs are corresponding. the inputs and outputs of the device, the control output is connected to the input of the first block of elements And, the group of control outputs is associated with a group of information inputs

0 of the control unit, the clock input is connected to the overflow output of the second counter, and the group of result inputs, the first group of inputs of the first block of OR elements and the output group of the test result of the device are connected to the output of the return code of the result register, controlling which information is read the inputs of the object parameter register, the evaluation register of the first and second memory blocks of the fault table, the health code evaluation unit, the inputs of counters, the second group of inputs of the first b The OR elements, the first group of inputs of the second block of elements AND, and the group of synchronization inputs of the result control block are associated with the synchronization outputs of the control block, the information output, indication outputs and the start input of which are the corresponding outputs and input of the device; the memory of the fault table is connected to the output of the first counter; the installation inputs of the meters

5 serve as the corresponding inputs of the device, the groups of outputs of the memory blocks of the fault table are associated with the third and fourth groups of inputs of the first block of OR elements, the output of which is connected to the information input of the evaluation register and

to the first input of the second block of OR elements, the second input of which is the information input of the device, and the output is connected to the information input of the object parameter register, the output group of which is associated with the fifth group of inputs of the first OR element block and the first group of information inputs of the code evaluation unit health, the synchronization input of which is connected to the output of the second block of elements And, and the second group of information inputs and the second group of inputs of the second block of elements And connected to the group of outputs of the register and.

In the proposed device, the links between the second AND block, the output register and the display and communication block of the control unit with the two memory blocks of the fault table, the registers and the second block of AND elements are saved, all other links between the known and newly introduced blocks are new . New connections include all connections with the first block of OR elements, i.e. the outputs of the first block and the second memory block of the fault table, the output of the object parameter register, the output of the result register and the output of the control unit with the inputs of the first block of OR elements, as well as the connection of the output of the first block of OR elements with the input of the evaluation register and the output of the register with the inputs of the second block And elements and a health code evaluation unit, connecting the output register of the result with the input of the result control block and the output of the control block with the inputs of the first block of the And elements and the control block, as well as the output block the control result to the input control block, the second counter outputs the result to the input control block. All new connections together with the newly introduced blocks provide the expansion of the device application area by simultaneous control of heterogeneous typical computing units. X

Figure 1 shows the structural diagram of the device; in phi, d.2 is a block diagram of the device with details of combinational units; fig.Z-same, the control unit of the result; figure 4 - the algorithm of the proposed device; Fig; 5 is the transition graph of the control unit; Fig. 6 is a block diagram of the control unit with the details of the transition control node; figure 7 - diagram of the switch; FIG. 8 is a diagram of the control code verification node; FIG. Fig. 9 is a block diagram of an encoder, a register, an AND node and a counter of a control unit; figure 10,11 - the first and

the second implementation of the pulse generator; in fig. 12 is a time sweep of the generator signals for the second embodiment; in fig. 13 - register scheme

evaluation and register of object parameters; on Fig - scheme of the register result.

FIG. 1-6 are the inputs and outputs: Co — zero state setting; Ci code entry; Ca - read the direct code ;.

Sz - reading the reverse code; C4 - adding 1 to the counter; Cs - synchronization of the first block of elements And 11 (1 BLSHI-11); Sat - unit input through the first block of elements OR4 (1BlSHILI-4) on РгО-5;

C - synchronization of the second block of elements And 6 (2BChI-6); Snatch - device stop signal after device shutdown; Sosh - a signal of transition chipper stopping the operation of the device; “2 device is OK; "2 device is defective; а о - search mode for faulty blocks and elements; a o - the mode of control of the health of the elements of computing equipment; and i - fault detection;

a 1 - no fault; AZ - the end of the input to the device table of fault functions; “3 - continuation of inputting the fault function table into the device; Ao, Ai, A2, ... A20 - control operators, meaningful meaning and a set of micro-operations in which are given in Table 3.

For a better understanding, the numbers of those blocks of elements that they

govern. For example, in block 15, the triggers 35 and 38 have control signals Co (35), Co (38), elements And 34, And 37, signals Ciis-1). Ci (37). ,

Device for finding faulty units

and the elements contain (Fig. 1) the first counter (MF) 1, the output of which is connected to the address inputs of the first 2 and second 3 memory blocks of the ROM fault table, the output groups of which are associated with

the third and fourth groups of inputs of the first block of the elements OR 4 (1 BLKHILI), the output of which is connected to the information input of the register 5 points (PrGO), the group of outputs of which is connected to the second group of information inputs of the second block of elements AND 6 (2БСХИ) and with the second group of information the inputs of block 7 evaluation code health (VO), the output of the second block of elements And 6 (2BlSHI)

connected to the synchronization input of block 7 evaluation of the health code (VO), the output of the first block of elements OR 4 (1 VLSIL) is connected to the first input of the second block of elements OR 8 (2 VLCIL). second-entrance

9 of which is the information input of the urban interface, and the output is connected to the information register of the parameter register 10 in the object (RGPO), the output group of which is associated with the fifth group of inputs of the first block of the OR elements (1BlSHLI) and the first group of information inputs of the code evaluation unit 7 health condition (BO), a group of outputs of which is connected to the group of inputs of the first block of I 11 elements (1 BL0xI), the output of which is connected to the information input of the result register 12 (РгР), the output of the direct code of which is connected to the display unit 13 (BI) and with a group 14 device test results, and the output of the return code is connected to the output group of 14 device test results, with the first group of inputs of the first block of elements OR 4 (TBLILE) and with the group of inputs of the result of the result control unit (BC) 15, which has information outputs 16,17 , indicator outputs 1; 8,19 and setup inputs 20-1,20-2, which are the corresponding outputs and inputs of the device, the clock input of the result control unit 15 (BK) is connected to the overflow output

a) second counter 21 (MF), having a setup input 22, which is the corresponding input of the device, controlling the output of the result control unit 16 (BK) connected to the input of the first block of elements 11 (1BLCA), the group of control outputs of the result control unit 15 ( BC) is associated with a group of information inputs of control unit 23 (CU), having a start input 24, indication outputs 25,26, information output 27, corresponding to the device input and output, with a group of synchronization outputs of control unit 23 (CU) counting inputs connected counters

1 and 21, the readout information inputs of the first and second memory blocks of fault tables 2 and 3 (ROM), the second group of inputs of the first block of elements OR 4 (1 BLXIL AND), which unload the information of the evaluation register 5 (RGO), read the information, first the group of inputs of the second block of elements Ib (2BlSHI), which control the reading of information, the inputs of block 7 for evaluating the health code (BO), register 10 object parameters (RGPO), register 12 for the result (РгР) and group of synchronization inputs for block 15 of the control unit (BC) , while the first counter 1 (MF) has a set General input 28-1, information output 28-2 and indicator output 29, which are the corresponding input and output of the device.

Blocks 4,6,8,11 device and element

unit 7 evaluation code health, unit 15

|. result control, control unit 23

typical and implemented serial LSI of

typical integral sets (for example, K155 logic). In particular, all registers 5, 10, 12 have a typical structure on static triggers,, allow reception of a direct code (when applying

0 of the signal C1), the storage and delivery of the forward one (Ca signal) or the reverse (C3 signal) code, while the initial (zero) state is set by the Co signal.

Read signal from a single (C2

5 and the zero (C3) outputs of the register triggers 5.10 are produced through the OR circuit (Fig. 1.13), and the single and zero outputs of the register 12 triggers are produced separately (Fig. 1.14).

0 Counters 1.21 are conventional counters of sequential summation of units, having, in addition, installation inputs 22.28 - 1, which allow entering the initial code in parallel. This type of meter is available in serial type logic sets.

The health code evaluation unit is (FIG. 2) n of the elements OR NOT

30.1, some inputs of which are connected to control output C7 (30) BU23, and others

0 is connected to the corresponding outputs of the evaluation register 5, the output of which is connected to the first input of elements And 30.2, the output of which is connected to the second input of the corresponding (each element

5 OR-NOT 30.1, and 30.2) an element OR-NOT 30.3, the output of which is connected to the input of the corresponding element AND of the first block of elements AND 11, and for any 1st element AND 30.2 the first input is connected

0 with the 1st output of the evaluation register 5 through the i-th scheme OR-NOT 30.1, and all the other outputs, Pr05 (for I 1,2n / ij), except i-ro, are given to (n-1) other inputs element i-ro

30.2, the corresponding 1st outputs of the second 5 block of elements AND 6 and the register 10 of the object parameters are the third first inputs of the elements OR NOT 30.3 of the evaluation block 7 (Fig. 2). , -.

The display unit 13 is implemented in the form of 0 n LEDs, each of which is connected to a potential single output of the result register 12. The indicators 18,19,25,26 are also implemented as LEDs, one for each output of the corresponding 5 unit. The indicator of the first counter is 29 co. It consists of m LEDs, where m is the number of counter bits.

Fault table memory blocks - permanent storage devices (ROM 2.3) - typical BIS ROMs with

4 erasing or ferrite ROMs for special control automation systems with increased requirements for mechanic-climatic modes of operation, as well as any types of ROMs depending on the type of control systems for a microprocessor system that is subject to troubleshooting. If the device for searching faulty blocks and elements is used only in a specific microprocessor system (therefore, it is necessary to write only one specific fault table), then it is advisable to use ROM with jumpable jumpers, since they have an increased fast action compared to other type BIS ROMs . For each ROM, the control unit issues two commands (Ci, C2). And in the first ROM (2) and the second ROM (3) the same fault table is written, but the record is written in such a way that the table is read in columns from the first ROM 2 and in rows of the second ROM 3. The address code for both ROMs is taken the same from the summing counter 1. In order to expand the field of application of the proposed device, instead of a ROM, a programmable logic matrix, a decoder, a register, a counter and other blocks of computing technology may also be included.

The result control unit 15 (FIG. 3) includes the first trigger T 31, the single input of which is connected to the clock input O Jmax) of the block, the second trigger T 32, the zero and single inputs of which are connected to the first 20-1 and second 20, respectively 2 installation inputs of the block, an input first element OR 33, whose inputs are connected to a group of inputs of the result of the block, and an output connected to the second input of the first element 34, output 34 and connected to the single input of the third flip-flop T 35, direct output T 35 connected to the first input of the second element And 36 and the indication block output 18, output AND 36 is connected to information output 16 of the block, simultaneously the output of the first element OR 33 forms a second serial circuit, and the output OR 33 is connected to the second input of the third element AND 37, the output of which is connected to the single input of the fourth trigger The T 38, the direct output of which is connected to the first input of the fourth element I 39 and the indicator output 19 of the block, the output 39 and connected to the information output 17 of the block, the direct outputs of the third T 35 and fourth T 38 of the flip-flops are also connected

respectively, with the second and third inputs of the second element OR 40, the output of which is connected to the control output of the block, the forward and inverse outputs of all the triggers (first T 31, second T 32, third T 35 and fourth T 38) form a group of control outputs of the block , while the signals of the inverse outputs of the flip-flops 35, T 38 form the signals oi, Oi, the direct outputs of the flip-flops T 35.38 - the signals “i,, the signals of the direct and inverse outputs of the flip-flop T 32 form the signals o, c, the signals of the direct and inverse outputs of the trigger T 31 form the signals oz, CQ, the first

5 inputs of all elements And (first And 34,

second and 36, third and 37, fourth and

39), the first input of the second element OR 40,

zero inputs of the first T 31, third T 35 and

Fourth T 38 flip-flops are connected to

0 group of block sync inputs.

The group of control outputs of block 15 is connected by a group of information inputs “o, 5), oz,“ 3, ”1,“ 2. "I, 02 of control unit 23 (БУ23), the group of sync inputs of synchronization of block 15 is associated with the group of synchronization outputs of control block 23: Co, Ci, C2, C3 (PrPi2), C7 (Б07, 2БлСхИ6),. Co, C1, C2, Cz (PrgP010), Co, C1, C2, Cz (Prg05), C1, C2 (1PZU2), C1, C2 (2PZUZ), Co, C2, C4 (Сч1), С, й

0 (Sch21), C5 (BK15), Co, Ci, C2 (BK15).

The clock input of the unit 15 is connected to the overflow output (j jmax) of the second counter 21 (Sch21), and the control output of the block (the output of the second element OR 40 C5 (40) is connected with the input of the first block of elements And (1BLC11).

The control unit 23 (BU23) (FIG. 6) includes an encoder 41 (W 41), to the output of which the information input is connected

0 register 42 (Prg42), the outputs of register 42 are associated with the group of inputs of the node node And 43 (BLHI43), the output of which is connected to the zero input of the counter 44 (Sch 44), the output of the counter 44 is connected to the information

5 the input of the decoder 45 (LH45), with the output of the decoder 45 is connected the second group of inputs of the control course check node 46 (Cx46) the first group of inputs of which is associated with the group

0 information inputs marked with symbols Oo,, oz, her, "1, az," 1, Q2 of the control unit 23 connected to the group of control outputs of the result control unit 15.

The OUTPUTS of the control code verification unit 46 is connected to a group of information inputs of the switch 47 (KMr47), whose outputs form a group of synchronization outputs of the control unit 23 and are connected to the second control input of the transition correctness control node 48 (BKP48) connected to one element input OR 106, and with the input governing the output of the node 48 of the control of the correctness of the transitions connected to one input of the element 105, the indication outputs 25,26 and the information output 27 of the node 48 of the control of the correctness of the transitions are corresponding outputs of the control unit 23, the first and second groups of information inputs of the control unit 48 transitions correctly connected to one and the other inputs 93-95 equivalence circuits, coupled to the outputs of counter 44 and the register 42,

One group of outputs of the control code verification node 46, labeled FI, is connected to the input of the encoder 41, another output group of the control code verification node 46, labeled F2, is connected to the fourth group of information inputs of the transition control node 48 associated with the inputs of the OR element 108, the outputs of the corresponding bits of the decoder 45, labeled with symbols Teo, Tai, TaiSt connected to the third group of information inputs of the node 48 control the correctness of the transitions associated with the inputs of the element OR 107, the output of the node 46 The checks of the control code marked with the MF symbol is connected to the second input of the first element OR 49, the output of which is connected to the zero input of the first trigger T 50, the inverse and direct outputs of which are connected to the first inputs of the first element And 51 and the second element And 52, and a single input is connected to the output of the control code check section 46, marked with the RP symbol, the outputs of the elements 51 and 52 are connected respectively to the counting input of the counter 44 and the input of the node elements And 43, the clock pulses for the operation of the control unit 2 ator 53 pulses (GI53) ,. three outputs of which are connected to the second inputs of the third element And 54, the fourth element And 55 and the fifth element And 56, the output of the third element And 54, marked with the symbol G2, is connected to the second inputs of the first and second elements And 51, And 52 and to the third input synchronization of node 48 to control the correctness of transitions associated with the zero input of trigger T102, the output of the fourth element AND 55, marked with the symbol n, is connected to the second synchronization input of node 48 to control the correctness of transitions associated with one input of element 103, the output of the fifth element And 56, p marked with the symbol G, is connected to the first synchronization input of the node 48 of the control of transition correctness associated with one input of elements AND 97, AND 98, AND IS NOT 109 and with the control input of the decoder 45, the first input of the second element OR 57 is connected to the inverse output the third trigger T 63, the zero input of which is connected to the start input 24, the second input of the second element OR 57 is connected to the error output of the transition control node 48, marked with the Sosh symbol and connected to the output of the And 103 element, the third input of the second element OR 57 is connected from the exit discharge decoder 45 marked with the BBB. at the same time, the inverse output of the third flip-flop T 63 is connected to the first input of the first element OR 49, with the control input of the encoder 41, marked with the symbol Co (42), with the input of the node of the elements And 43 marked with the symbol Co (44), with the first control input of the switch 47, marked with the symbol AO, with the first control input of the node 48 for controlling the correctness of transitions, is associated with. with the input of the element OR 106, with one synchronization output of the synchronization output group of the control unit 23, marked with the symbol Co and the input of the element

58 of the first delay element included in two series-connected delay elements, including HE 58, NOT 59, HE 60.4NE 61, the output of the HE element

59 of the first delay element is connected to the second control input of the switch 47, labeled Aig, the output of the NOT element 61 of the second delay element is connected to the single input of the third flip-flop T 63, the direct output of which is connected to the single input of the second flip-flop T 62, to the zero input of which the output of the second element OR 57 is connected, the direct output of the second flip-flop T 62 is connected to the first inputs of the third element And 54, the fourth element And 55 and the fifth element And 56.

The outputs of the node 46 check control

Ai code, A2Ais.Aao, Ao output. From input 24,

start, the inverse output of the third trigger T 63, the output A 19 from the output of the element NO 59 of the first delay element is connected to the inputs of the switch 47 (FIG. 6).

The switch 47 (Fig. 7) makes the distribution of micro-operations among the elements and blocks of the search device that execute the given control operator Ao.Ai, A2, Az, ..., A19, A20 (see table 3) and ecstrate out of 32

of elements OR 47.1, OR 47. OR

47.32.

The inputs of the elements OR 47.1–47.8 are connected to the output of the AO, while the OR output 47.1 forms the signal Co (1), the output OR 47.2 is the signal Co (15), the output OR 47.3 is the signal Co (5), the output OR 47.4 is the signal Co (10 ), output 47.5 - Co signal (12), output OR 47.6 - Co signal (35), output 47.7 - ео signal (38), output 47.8 - Co signal (104).

With the output AI, the inputs of the elements OR 47.11 are connected. OR 47.17, OR 47.18, OR 47.30, output OR 47.11 forms the signal Ci (12), output OR 47.17 - signal C2 (5), element output OR 47.18 - signal C2 (10), output OR 47.30 - signal C5 (40 ).

With the output A2, the inputs of the elements OR 47.9, OR 47.14, OR 47.29 are connected, the output OR 47.9 forms the signal Ci (5), the output OR 47.14 - the signal Ci (34). output OR 47.29 signal Sz (12).

The input of the element OR 47.5 is connected with the output AZ, the output OR 47.5 forms the signal Co {12).

With the output of the A4-connected inputs of the elements OR 47.11. OR 47.17, OR 47.18, OR 47.27, OR 47.32, output OR 47.11 forms signal Ci (12), output OR 47.17 signal G2 (5), output OR 47.18 - signal C2 (10), output IL AND 47.27 - Signal Сз (5 ), OR output 47.32 - StSb signal),).

The inputs of the elements OR 47.10, OR 47.15, OR 47.29 are connected to the output AS. output OR 47.10 forms the signal Ci (10), output OR 47.15 - signal Ci (37). output OR 47.29 signal Sz (12).

With the output Ab, the inputs of the elements OR 47.3, OR 47.5, OR 47.6, OR 47.7, OR 47.12, OR 47.13, OR 47.16, output or 47.3 form the signal Co (5), OR 47.5 - the signal Go (12), OR 47.6 - the signal Co (35), OR 47.7 - Co (38) signal, OR 47.12 Ci (2) signal, OR 47.13 - Ci (3) signal, IL AND 47.16-C2 signal (1).

With the output Ay, the inputs of the elements OR 47.9, OR 47.18, OR 47; 20 are connected, the output or 47.9 forms the signal Gi (5), the output OR 47.18 - the signal C2 (10). output IL AND 47.20-signal C2 (2).

The inputs of the elements OR 47.3, OR 47.14, OR 47.29 are connected to the output AS: output OR 47.3 forms the signal Go), output OR 47.14 - signal Ci (34), output 47.29 - signal G3 (12).

G output Ad is connected to the inputs of the elements OR 47.9, OR 47.29, the output OR 47.9 forms the signal Gi (5), the output OR 47.29 signal G3 (12).

The AYU output connects the inputs of the elements OR 47.5, OR 47.9, OR 47.21, the output or 47.5 forms the signal Go (12), the output OR 47.9 - the signal Gi (5), the output 47.21 the signal G2 (3).

G output All connects the inputs of the elements OR 47.8. OR 47.11. OR 47.18,

OR 47.27, OR 47.32, output OR 47.8 forms the signal Go (104), OR 47.11 - the signal Gi (12). OR 47.27 - signal G3 (5), OR 47.32 signal G7 (6), GY (30), OR 47.18 - signal G2 (10).

0 G output Ai2 connected inputs of the elements OR 47.16, OR 47.19, or 47.22. OR 47.23, OR 47.24, output OR 47.16 forms the signal G2 (1), OR 47.19-signal G2 (12), OR-47.22 - signal G2 (36), OR 47.23 - signal G2 (39), OR 47.24- signal G2 (105).

G output Ai3 connects the inputs of the elements OR 47.4, OR 47.12, OR 47.13, OR 47.16, output OR 47.4 forms the signal Go (10), output OR 47.12 - signal Gi (2), output 47.13 - signal Gi (3), output IL AND 47.16 signal l G2 (1).

G output Ai4 connects the inputs of the elements OR 47.10, OR 47.21, the output OR 47.10 forms the signal Gi (10), the output OR

5 47.21-signal G2 (3).

G output Ai5 connected inputs of the elements OR 47.11, OR 47.17. OR 47.18, OR 47.30, OR 47.32, output OR 47.11 forms the signal Gi (12), output OR 47.17 0 signal G2 (5), output OR 47.18 - signal G2 (10), output OR 47.30 - signal G5 (40), output OR 47.32 - signal G7 (6), G7 (30).

G output Ai6 connected inputs of the elements OR 47.11, OR 47.27, OR 47.28,

5 OR 47.30, OR 47.32, output OR 47.11 forms the signal Gi (12); output OR 47.127 signal G3 {5), OR 47.28 signal G3 (10). OR 47.30 - signal G5 (40), OR 47.32 - signal G7 {6), G7 (30).

0 G output Ai7 connected inputs of the elements OR 47.5, OR 47.6, OR 47.7, OR 47.8, output OR 47.5 forms the signal Go (12), OUTPUT 47.6 - signal Go (35). output OR 47.7 - Go signal (38), output OR 47.8 5 Go signal (104).

G output Ai8 connected inputs of the elements OR 47.25. OR 47.26, exit OR

47.25 forms the signal G41), output OR

47.26- signal G4 (15).

0 G output Aig connected inputs of the elements OR 47.9, OR 47.31, OR 47.9 output forms the signal Gi (5), the output of the AND L AND 47.31 - signal G6 (4).

G output A20 connected inputs of the elements OR 47.15, OR 47.29. output OR 47.15 forms the signal Gi (37). output OR 47.29 signal rz (12).

Node check control code 46 (Fig.8) implements the Boolean functions of the table. 1 control unit BU23 and consists of two

And 64, And 65 elements, the first inputs of which are connected to the output of the decoder 45, marked with the symbol wav, the second input And 64 connected to the output "2, and the second input And 65 with the output ig, output And 64 forms the signal Ab and is connected simultaneously with the first the input element OR 66, the second input of which is connected to rais, and the output forms the signal 17 (Ab) and is connected to the input of the sequence of elements OR 67, NOT 68, then the output OR 67 forms the RP signal, and the output NOT 68 Signal Sc, output Tai3 connected to the first inputs of the elements I.69, And 70, And 71, And 72, with the output of the element And 72 connected to the first th input of the OR gate 73, the other three inputs of which are connected outputs of AND 65, Tai4i and 70; the second inputs And 69, And 71 are connected to Oi, and the third from%, the fourth input And 69 is connected to az, and And 71 saz, tayu is connected to the first input And 74; оъ with the second input And 74, and (% with the second input And 77, the first inputs of the elements And 76, And 77, And 79 are connected to the melt, the second inputs And 76 and And 79 are connected to Oo, and the third inputs And 76, 77 with at, a “i with the third inputs I 74, I 79, with the fourth input I 74 connected by oz, and one with the fourth input I 79, the outputs I 76, I 77 form the signals A9i Ai5, and through the circuit OR-HE 78 form the signal fii, and the output OR-NE 78 is connected to the fourth input OR 67, the second and third input AND 70 are connected to the inputs (% and (%, and the second input AND 72 with "o. outputs And 65, And 70. And 72 and gam are connected through the element OR 73, the output of which is connected to the second input OR 67, while the output OR 73 forms a signal f6 (Al2).

The output AND 71 forms the signal Ar and together with the output AND 74 through the element OR 75 forms the signal fi4 (Ai7), which is connected simultaneously to the third input OR 67, the outputs And 69, And 79 through the element OR 80 forms the signals fi5 (A18), and the OR 80 output is connected to the OR input of the 67, to the sixth input of which is connected fo tab. In addition, the node 46 checking the control code contains the elements And 81, And 82 ,, .., And 90, with the first inputs And 81, And 83, And 85. And 87, And 90 are connected with Co, and the first time inputs And 82 , And 84, And 86, And 8B, And 92 s with, the second inputs And 81, And 82 are connected to the rag, the second inputs And 83, And 84 are connected to the ran, the second input And 85 from the hectare 12, the second inputs And 86, And 87 with Ga7, the second inputs And 88, And 90 with hey, while the outputs And 81-And 86 form, respectively, the signals Az, Ai4, AU. Ai6, All, Ai3, and the outputs And 87, And 88 are combined by the element OR 89 and form the AT signal, the output And 90 and gao are combined by the element OR 91 and form the signal I, the second input And 92 is connected to rai2, and the output And 92 forms signal Aao.

The control unit 23 comprises a node 48

controlling the correctness of the transitions (Fig.6) from one state to another. Based on the operation algorithm of the control unit BU23 of FIG. 4), a transition graph (FIG. 5) is obtained. Ana of FIG. 5 shows that transitions from one state to another, other than the counting mode, are performed in the state of 0.6, 7, 14, 15 (Table 2).

As can be seen from table 2, except for transitions 6-

O,,, for all other transitions, in the two states ai (t) and ai + i (t + 1), at least three bits out of four in memory register 42 and counter 44 of the control unit 23 must be identical.

This property is used to construct the node 48 for controlling the correctness of the transitions (Fig. 6), which contains circuits 93-96 equivalents, whose inputs are connected to the direct outputs of the driggers of the register 42 and

the counter 44 and form the first and second groups of information inputs of the node, the outputs of the circuits 93-96 equivalence with different combinations of three of the four outputs associated with the second inputs of the first element And 97, the second element And 98 and the third element And 99, the outputs of circuits 93,94 , 96 equivalence connected to the second input element And 97, the outputs of circuits 93,95,96 equivalence connected

with the second input element And 98, the outputs of circuits 94,95,96 equivalence connected to the second input element And 99, the outputs of the first to third elements And 97-99 are connected to the inputs of the element OR-II

100, the output of which is connected to the second input of the fourth element I 101, the output of which is associated with the single input of the first flip-flop T102, the zero input of which is connected to the third synchronization input of the node and the direct output to the first input of the fifth element I 103, the second input of which connected to the second synchronization input of the node, and the output from the error output of the node and to the single input of the second trigger

T 104, the inverse output of which is connected to the first input of the sixth element 105, the second input of which is connected to the control input of the output of the node, and the zero input is connected to the output of the first element OR 106, whose two inputs serve as the first and second control inputs of the node , the direct output of the second flip-flop T 104 and the output of the sixth element And 105 are two indication outputs 25.26 and

information output 27 of the node, a group of inputs of the second element OR 107 and the third element OR 108 are connected to the third and fourth groups of information inputs of the node, the outputs of the second element OR 107 and the third element OR 108 are connected to the first and second inputs of the AND-NOT element 109, the third input which and the first inputs of the first element And 97, the second element And 98 and the third element And 98 are connected to the first synchronization input of the node, the output of the element AND NOT 109 is connected to the first input of the fourth element And 101.

The encoder 41 of the control unit 23 (FIG. 9) includes six elements OR 110.1,110.2, ... 110.6 with a number of inputs equal to two (OR 110.1,110.2,110.6) equal to three (OR 110.5) and four (OR 110.3, 110.4), connected in a matrix scheme with the outputs of the node 46 verification of the control code, marked with characters

fo, fRf7, f14f15.

Figure 9 shows the structure of register 42, consisting of the flip-flops T 42.1, T 42.2, T 42.3, T 42.4 and the setting circuit of the register Prg42 of the control unit 23 into the zero state via the OR element 112, one input of which is connected to the check output 46 the control code, the signal Co (42) and the elements OR 110.1, ..., OR 110.6 of the encoder 41 are given by the signal Co (42). It also shows the structure of the node element And 43, synchronized by the output G2 of the element And 54 of the control unit 23, and the circuit set to zero (initial) state of the triggers of the counter 44 of the control unit 23

through the elements OR 111.1 OR 111.4

node elements And 43 signal SS (44).

Counter 44 is a four-bit binary counter; To the counting input of which signals are received And the element 51 of the control unit 23, and to the single inputs of the flip-flops T 44.1, ..., T 44.4 signals from the outputs of the node of the elements And 43. The outputs of the counter 44 are connected to the inputs of the decoder 45 (FIG. 6).

Fig. 9 shows the connection of the counter 44 with the node of the elements And 43. The counter 44 can be implemented on an integrated microcircuit of the type K15IEIE7 or of the type KM155IEO7.

The pulse generator 53 consists (Fig. 10) of a clock generator 113 (GT), a counter 114, and a decoder 115, the first outputs of which provide for the issuance of periodically repeated time-separated pulses ir, TI, G2. This scheme is the simplest and requires a typical two-bit counter 114 and a decoder 115 for two inputs and four outputs.

However, the disadvantage of such an implementation of the G53 (albeit acceptable) is the omission of a clock, and the duration of the r, n, T2 clocks is the same, although each of them ensures clocking of circuits of different logical depth. So. By the signal PG and P, the elements 51 51 and 52, adding 1 to the parallel code entry in the counter 44, are also reset to the initial state T 102 and the synchronization And 103 by the transition control node 48 (FIG. 6), while the signal t closes the control code check section 46 and the node 48

5 controls the correctness of the transitions along the chains OR 107, AND-NOT 109, AND 97, And 98, And 99, OR 100, with the result recorded at T 102. The total logical depth of the nodes KCh46 and BKP 48 for the signal g is equal to ten, and for TI and T2 signals are two, i.e. from the point of view of speed, it is permissible to use the GI 53 variant of the GI 53 scheme, in which the first pulse is generated, t is lOt, and the other two (n, Ta) are 2t, where t is a conventional unit of time, equal to the delay of one elementary logical element of the type AND, OR, NOT (Fig. 12). So a variant of implementation, GI53 is shown in Fig. 11. Due to the delay of 4t elements NOT 116-119 from the periodic signal x GT 113 and on the element IT 120 the element 121 and the signal TI is formed, which is equal to the duration of 3r {since TI xj, z x + 3t), and the signal-T2 is formed by the elements HE 122, ..., HE 125 due to a TI delay of 4t. Both the one and the other implementation of the G53 is implemented by integrated circuits. In particular, the logic circuit of FIG. And can be implemented on 2 buildings

0 of a typical K155 logic, since up to 8 NOT circuits are located in one package. N On Fig.13, 14 presents blocks 1 6130.

With the exception of display units and

5 permanent storage devices 2,3 the whole device for searching faulty blocks and elements can be executed both on the elements of typical logic, and in the form of custom or semi-custom large integrated circuit.

The operation of the search device 1; 1 faulty blocks and elements is carried out in the sequence determined by the algorithm of FIG. 4, after the filing

5 signals Start i24 (it is desirable that the Start 24 contact be bounce-free, the schemes of such contacts are known). However, in the presence of bounce, the device as a whole will work correctly, with the only difference that the first K pulses during bounce will cause the device to work, which will stop with the next pulse U, the operation will start anew, i.e. in fact, from K pulses, only the last one will finally launch the device into operation). It is set to the initial state BU23 (Fig. 6) (T 50, T 62. T 104, Mid 44, Pr 42, T 31) and the search device itself (Fig. 2) by the AO operator (Table 3) due to the installation of the initial (zero) state of the MF 1, MF 21, registers 5,10,12, triggers 35.38 in the result control block 15 (FIG. 3) and trigger T 104 in the transition control node 48: Through the delay 2t with the signal of the operator Al9 БУ23 (Fig. 6.2, Table 3) the recording 1 is made (signal Ce (4), C1 (5)) on Pr05, the code of which after A19 becomes equal to 011 ... 1. According to the algorithm of the proposed device for searching faulty blocks and elements, if the parameter code in RGPO 10 is 000 ... O, and the column and row codes of the fault table are the same and equal to 011 ... 1, then the result of the operation of the entire search device should be code 111 .. .1 on the result register of PrP12 and BI13. This test check is carried out as a result of executing the A1-AS operators (Fig. 4), first reading the code (A1) of the registers 5,10 through the evaluation unit B07 and through the elements And 11 (Fig. 2), the intermediate result is recorded in PrPP12, while for the passage of the elements of AND 11 a pulse Co (40) is fed from the element OR 40 BC15 (Fig. 2.3). Then (A reads the reverse code of PrP12 and censuses it on Pr05 and checks BK15 (signal Cl (34)): whether there is at least one unit on PrgP12. The result is stored in T 35 as a single (one) or zero state. Operator A3 sets up the zero state of PrP12, preparing it for reception of the next code. Operator A4 reads the forward code of PrGRYu, Pr05 and the reverse Pr05 code through AND 6 elements (C7 (6) signal), when the OR-HE30.1 is disconnected I30.2 B07 (signal)) with the result recorded on PrPP12 (signal C1 (12)), with the passage of the elements in And 11 provides a signal of a single arm T 35 (fig.Z), if at the previous step of operation of BU23 in the intermediate result there was at least one unit (E1).

. Operator A5 records the readout of the PrgP12 code (signal C3 (12)) and receives the convolution result fToro on T 38 by the code OR 33 BK15. On T 38 |, 1 is fixed when the PrP12 code consists of only 1, i.e. 111 ... 1.

At the same time (in parallel), the signal C1 (10) of the operator Ab is used to receive the object parameter code on the rgPU. Then a T38 status check is made: whether it really did not go to state 1 ("1 - 1" if). If this happens ((% 0), then the search device itself is faulty, operator A12 of FIG. 4, Table 2 is executed) and the operation is terminated. Operator A12 reads into the external microprocessor system the contents of counter 1, result register 12, 6K15 T 36 and T 39 flip-flops, T104 error latch trigger, and prepares an automatic shutdown of the GI53 pulse generator with the Start signal.

If, on the other hand, a test check gives a strong result, then go to the Ab operator. Note that during the test check, with the exception of the 1PZU2 and 2PZUZ, the operation of all blocks and all connections of the proposed search device is checked.

Operator Ab sets the initial state of Pr05, PrгP12 and BK15 (35.38) and is pro-. emits the writing of the contents of Sch1 to the address registers of the ROM2.3 (which is included in the ROM2.3 and is not shown in the diagrams of Fig. 2.3). Then a check of the logical condition Oo ((XG 1) is performed, if the proposed device is operated in the main mode — the search for faulty blocks and elements). If% 1, then the contents of 1PZU2 and WGPU are read and written to Pr05 (operator t), then THEN; operation A-1 (Table 2) is the second — obtaining an intermediate result on PrgP12 and BK15 (T 35), after which the operator Aw generates a check of the intermediate result (similarly to operator A2 in terms of signals C3 (12), Ci (34)) on BK15 (T 53) and with a signal Co (5) sets to the initial state Pr05, thus preparing it to receive the code from Prg12. The logical operator "i checks whether there is at least one 1 (although there is one malfunction), if there is, then a transition is made (operators A9-A13) to the calculation of numbers of faulty blocks. At the same time, the A9 operator performs a rewrite of the reverse PrP12 code on Pr05, the AU content 2PZU (direct code) operator is also recorded on Pr05, while sequentially writing the contents of PrgP12 and the PZUZ to the same register Pr05, it performs the IL operation AND, since Pr05 is preset to O by Operator A11, completely analogous to A4, except for the added signal Co (1Q4) - no error in the operation of the proposed device, the final result is calculated and output (Al result outside a null circuit with the operation of the control unit BU23 due to the disconnection of the pulse generator 53 (Fig. 4,6). If, after the operator As, checking d indicates that it is on 0, then OQ is checked - is this not the last row (column) of the table Failures (i Jmax). IF 05 1, THEN all checks are over, the operator Ai7 sets the zero state of the T-104 latching trigger, the result register PrPP12, BK15 and goes to the operator Ai2.

If 03 O, then to the contents of Cm 1 and Sch21 is 1 (A18) and the program is repeated from operator A6

The fact that, in the basic mode, the number of the faulty block or element is actually found in the object's parameter code, we can see by example: let the test function table for the device under test be given in the form of table.4.

We form the code of the parameters of the object in the form of a logical multiplication of columns 4 and 12, which obviously corresponds to two faults at the same time and make sure that the proposed device will allocate faulty blocks in accordance with the described structural algorithm of the structure.

Then the code of the object's parameters takes the form:

х ° 1 х х х ° 4х% хОбх ° 7х% х ° 9х ° Юх ° 11 х ° 12х ° 13 1 11000001 11 00

Let the parameter code of the object be recorded already in RGPO 10, 1PZU2, 2PZUZ contains the object TFN, and on Sc21 it is set jmsxmaximal number of columns (rows) of the TFN by the operator through the input, and the test check gives the result А2 1. Then there is a transition to the operator Ab (Fig, 4 ), which initializes the triggers 35, 38 BK15, registers Pr05, PrgP12 and records the first address of the column and the rows of the Fault Function Table (TFN) in the address registers 1 PZU2, 2 OPSR from the contents of Sc1. Let the logical condition ob 1 be fulfilled, corresponding to the operation of the device in the search mode for faulty blocks. Then, operator A is executed, reading the object's CBD parameters from PROGU and the code of the first column of PSTN from 1PZU2 and writing it to Pr05, then the AI operator reads the code of the first column from PROG5,

the code of the parameters of the object W3 and their entry in PrPP12,

As a result of the execution of the A1 operator, an intermediate result is obtained on

PrP12. The AO operator sets up the initial state Pr05, reads the inverse of the Prг12 code, writes it to BK15 (T 35), forms the logical operator i, which checks for the presence of at least one.

Nick in reverse code. In this case, ai О (table 5). Then BK15 (T 31) checks the condition OQ - is this not the last row (column) of TGNT (jmax). in our case, oh, oh, since

the column does not last, then to the contents of the counters Cch1. Sc21 is added 1 (operator ASH).

A cycle involving operators and conditions l - Ay - l -.

repeats until the fourth column is entered, i.e. for the first, second, and third columns of TFN (Tables 5–7). After entering the fourth column of TFN, the operator A forms “i 1, i.e. presence of at least

one malfunction (tab. 8). Then a transition is made (operators A9-A12) to the calculation of numbers of faulty blocks.

Operator A9 will produce a census about; of the RSrP12 military code on Pr05, operator А10

will write the code of the fourth line of PSTN on Pr05, while OR operation of the code of the fourth row of the CTF and the reverse code of PrP12 recorded on Pr05 by the operator A9 is carried out bit by bit by setting the PrgP 12 state to zero (Table 9). The return code will be read from Pr05.

on the second entrances of 2BLSnI6, on the first entrances

which receives a synchronization signal

СХ6) from БУ23. Output signals 2БЛСхИ6

arrive at the synchronization inputs of the elements OR-NOT 30.3 507, to the first inputs of which the object parameter code is read from PRPU. In this case, the signal CXRD) to the second-inputs of the elements OR-NOT 30.3. Zero signals from the chains of the elements OR-NOT 30.1-I30.2 BO7 are read out. ;

Elements 11 of the 1BLSN are synchronized by the CS (40) SK15 signal obtained when implementing the operator A8. The results of calculating the numbers of faulty blocks with the output of the elements AND 11 1 BLSxI are recorded on ProgP 12 (Table 10).

The operator A12 produces the issue of the result on the display unit BI 13, on

A visual indication of the failure of the fourth and twelve blocks appears.

When OO O, the operation of the proposed device in the expansion mode

fields of application by simultaneous control of dissimilar typical units of computer technology. The operating mode (ao f O or o -1) is set by the opera: o. torus on the inputs 20-1 and 20-2. For a review of the control mode parameters of storage devices.

Memory monitoring is performed using reference memory. A code is written into the verifiable and reference memory and the check reading is determined by Marriage-Year.

In the proposed design of the device for searching for faulty blocks and elements, the reference and verifiable ROM with pre-recorded information on the same programmer should be installed in place of the first and second ROM2 and ROM. Due to possible malfunctions in the checked ROM (or operational memory), starting from some address, the codes of the reference and the checked memory will be different in the event of a malfunction.

According to the algorithm (Fig. 4), with "0 0 by the operator ATS, it is reset to the initial state of FGVU, since the code of the object parameters is not required in this mode and the address code is written to the Fr address of the first and second memory. Operator A reads the code of the reference ROM on Pr5 and the register of the ROM to be checked on the PrgPU register (operator A1.4 for the same address. Operator A15 uses Andr 6 to write Pr5 code and PrgP code on Pr проP12. 11, signal C5 (40) is applied. Operator A16 performs the same action, but only for reverse codes Pr05 and PrgOOJ. Thus, PrrP12 forms the equivalence function vj ai bi-b ai bi ,, 2, ..., n}, where ai and Ы - the value of the i-ro bit of Pr05 and RgPU. When performing the operators А15 / А16on one, the inputs of the I / 6 elements go mc is the sync signal C7 (6), and on one of the inputs of the elements OR NONE 30.1 there is a signal C7 (30), in which zero signals are fixed at the outputs of the elements H30.2.

 Consequently, if the codes of the reference and the checked ROM are the same, then the code of one 1, i.e. 111 ... 1. Operator А20 (СЗ (12), С 1 (37)) reads the reverse code РгР12 and writes the result to T 38. T 38 will appear in state 1, if on РгР12 all 1. By operator А20, after checking "2 (VI) either fixing the error (A12), or checking j jmax.

Note that instead of the RAM (operative or permanent), a combinational circuit or a programmable logic circuit can be included in place of the checked ROM.

matrix (PLA). At the same time, in the reference memory, the correct combination of output codes is pre-recorded for each input combination, and when installing the CSX or PLA, the control signal of the BU23 is not connected to them, since their operation is determined by the appearance of external (relative to the CSX or PL M a) signals at their inputs from Sch1.

In the same way, counters can be checked, and the contents of the MF will be overwritten, 1 unchecked counter with the same signal (C 1 (1)), and in the reference memory in this case the sequence of counter codes must be recorded.

When implementing the algorithm (figure 4), the BU23 operates in this sequence. Before giving a signal (input 24), the mode of operation (a o 1 or o o 0) is set to inputs 20-114 or 20-2, and an additional code of the maximal number of ohts of columns in the fault table ( for the main mode) or the number of tested combinations (for the additional mode).

After Start 24 through the item

OR 57, the installation of the BU23 in the initial state (T 50, T B2, WG4.2, Mid 44,

T 104, T 31) and through the delay 4t signal

unit arm T 62 connects GI53. The first impulse r from the element And 56 is the survey of the CCX46 via the DSL45. Since BU23 was previously in zero

state, then according to figure 5 (transition graph БУ23 of figure 5 is obtained in strict accordance with the algorithm of figure 4) KSx4b outputs the signal A1 and sets T 50 through the OR 49 circuit to the zero state. This work sequence will be maintained for any i-ro state (Fig. 5). At the same time, the same signal TW Pr42 records the new state of the BU23 at the outputs of the CCX46, which are labeled with the F1 symbol, if (as shown in FIG. 5) this change of state is not achieved by a simple counting. In the same case, in the BKP 48, the trigger T 102 will detect, by the signal g, whether the transition to the new state is correct, and before changing this state -:

Neither signal TF 150 will be set to one. Next comes the impulse TI, which checks the status of the trigger T 102 and, if there is no error in the transition, the rate of operation of the BU23 is not disturbed.

If an error is detected, then a signal. Sosh, operation of BU23 is suspended. .

 there was no error, then a change in the operation of BU23 occurs only at the T2 signal. In this case, the signal G2 occurs to change

The state of Sc 44, either by adding 1 through AND 51, or by entering a parallel code Pr42 through ULS2 by the signal I 52. After completing the series of pulses r, n, G2 on Sch44, the New state and the operation of the BU23 repeats with the arrival of A new series of pulses g, ri, T2 according to Fig.4.5.

The external information outputs of the proposed device allow the control results to be transferred to external systems for automatic decision making.

Claims (2)

Claim 1. Inventory of faulty blocks and elements, containing two memory blocks of the fault table, register evaluation, health code evaluation unit, object parameter register, first block of AND elements, result register, control block and display unit, whose input is connected to the output of the direct result register code, whose information input is connected to the output of the first And block block, group the inputs of which are connected to the group of the evaluation unit of the health code, characterized in that, in order to expand the field of application of the device by simultaneous monitoring of heterogeneous typical blocks of computer technology, two and a counter, two blocks of OR elements, a second block of And elements and a result control block, installation inputs, informational and indication outputs of which are the corresponding inputs and outputs of the device, a control output connected to the input of the first block of And elements, a group of control outputs - from rpynnoi information inputs of the control unit, the clock input is connected to the overflow output of the second counter, and the group of result inputs, the first group of inputs of the first block of OR elements, and the output group of the test result are devices va is connected to the output of the return code of the result register, which controls the reading of information whose input controls the reading of information, the inputs of the object parameter register, the evaluation register, the first and second memory blocks of the fault table, the health code evaluation unit, the counting inputs of counters, the second group of inputs the first block, the OR elements, the first group of inputs of the second block of the AND elements and the group of synchronization inputs of the result control block are associated with the group of synchronization outputs of the control block, information output. the indicator outputs and the start-up input of which are the corresponding outputs. dami and device input, address inputs of the first and second memory blocks of the table faults are connected to the output of the neW meter, the installation inputs of the meters serve as the corresponding inputs of the device, the groups of outputs of the memory blocks of the fault table are connected with the third 0 and fourth rounds of the inputs of the first block of OR elements, the output of which is connected to the information input of the evaluation register and to the first input of the second block of OR elements, the second input of which is ow -. 5 is the information input of the device, and the output is connected to the information input of the object parameter register, the output group of which is associated with the fifth group of inputs of the first block of elements 0 OR and with the first group of information inputs of the health code evaluation unit, whose synchronization input G1 is connected to the output of the second block of elements AND, and the second group of information inputs and the second group of inputs of the second block of elements AND are connected to the group of outputs of the evaluation register. 2. The device according to p. 1.0 tl and ch and y with the fact that the control unit of the result contains two elements OR, four elements AND and four triggers, zero and single inputs of the second trigger connected respectively to the first and second installation the block inputs, direct and inverse outputs of all triggers make up the group of control outputs of the block; a group of synchronization inputs of which are associated with the first inputs of all AND elements, with the first inputs of the second OR element, and with zero 0 inputs of the first, third and fourth triggers, the single input of the first trigger is connected to the clock input of the block, the group of result inputs is connected to the inputs of the first OR element, the output of which is connected to the second inputs of the first and third elements I. The outputs of which are connected respectively to the single inputs of the third and the fourth flip-flops, the direct outputs of which are respectively connected with the first inputs of the second and fourth elements of the AND, with the second and third inputs of the second element OR, and with the indicator outputs of the block, the output s of the second and fourth elements and are associated with 5 information outputs of the block, the output of the second element OR is connected to the control output of the block. H. The device according to Claim 1, of which is that the control block contains an encoder, a register, an AND node, and a counter. decoder, control code verification node, switch, transition control node, two ILW elements, three flip-flops, five AND elements, a pulse generator and two series-connected delay elements, the output of the second delay element is connected to the single input of the third trigger, zero input which serves as a block start input, the direct output is connected to the single input of the second trigger, and the inverted output to the first inputs of the first and second OR elements, to the input of the first delay element, to one of the outputs of the group synchronization of the block, to the control input of the encoder, to the input of the node of the elements I, to the first and right inputs of the switch and the node controlling the correctness of the transition, the output of the first delay element. connected to the second control The switch input, the outputs of which form a group of synchronization outputs of the block and are associated with the second control input and with the control input of the output of the transition control node, whose information and indication outputs are connected with the corresponding ones in the inputs of the block, first and at The torus of information inputs is connected to the outputs of the counter and register, three inputs of syncnization are connected to the outputs of the fifth, fourth and third elements AND, the third and fourth groups of information inputs - with the first group of outputs of the check code control node and with the outputs of the corresponding decoder bits , error output - with the second input of the second element OR; the third input KOTpJDOrO is connected to the output QOOT, the corresponding bit of the decoder, and the output to the zero input of the second trigger, the direct output of which is connected to the first inputs of the third-fifth elements And, the second inputs of which are connected to the outputs of the pulse generator, the output of the first the OR element is connected to the zero input of the first trigger, the inverse and direct outputs of which are connected to the first inputs of the first and second elements AND, and the single input, the second input of the first element OR, and the input of the encoder are connected to the corresponding outputs of the test node the control code, the group of outputs of which is associated with the group of information inputs of the switch, and the first and second groups of inputs Y with the group of information inputs of the block and with the outputs of the decoder. The information and control inputs of which are connected respectively to the outputs of the counter and the fifth element I, the counter input of the counter is connected to the output of the first one. And, and the zeroing input - with the output of the node of elements And, whose input is connected with the output of the second element And, and the group of inputs; - with register outputs whose information input is connected to the output the encoder, the second inputs of the first and second elements And connected to the output of the third element I. 4. The unit according to the item 3, excl and moreover that y, the control of the correctness of the transitions contains four equivalence schemes, six AND elements, an element, two Triggers, three OR elements and the NAND element, the output of which is connected to The first input of the fourth element is And, the first and second inputs are with the outputs of the second and third elements OR, and the third input and the first inputs of the first and third elements are And with the first synchronization input node, the second inputs of the first and third ele: cops, are associated respectively with the outputs of the first, second and fourth circuits equivalence, first, third and fourth equivalence schemes and second, third and the fourth equivalence schemes, the inputs of which form the first and second groups of information inputs of the node, the outputs of the first and third elements AND are connected to the inputs of the IL-AND-NOT element, the output of which is connected to the second input of the fourth element of the AND, whose output is connected to the single input of the first trigger, the zero input of which is connected to the third synchronization input of the node, and the direct output - to the first input of the first element And the second the input of which is connected to the second input node synchronization, and exit - with exit node errors and with a single input of the second a trigger whose zero input is associated with the output of the first element OR, and the inverse output with the first input of the sixth element AND, the second input of which is connected to the control input of the output of the node, and the output and direct output of the second trigger are informational and two indicator outputs of the node; groups of inputs of the second and third elements OR are connected to the third and fourth groups of information inputs of the node; two inputs of the first the OR element serves as the first and second control inputs of the node .fo p A fg Qr f, -00 f ai, 08 f 5 "-IC t,) f4 b. A, H A, s X. fg. + Uo & a ,,, +., O + 5 :, - + Aj, 3 Ab (Ag, 9, A, A, A o (:; gatsA 2 f l –c 0 Z f – o 3 l – o 7 A 4, 5 0 (Y, to, 0 fn Ai8 "Xg aj + ta gf, & a - iM C (o; o2a, 5 A fg a, 2o ° Table 2 2 2,, 5 + o (b52 (Oz 0.0 A set of micro-operations N2№ Stock (1.21,5.10.12,35,38,104) C2 (5.10) Ci (12) C5 (40) Sz (12) Gi (34) Ci (5) Co {12) C7 (6.30) C2 (10) C2 (5) Cz (5) CiCl2) Cz (12) Ci (37) Ci (10) Co (5.12.35.38) C2 (1). Ci (2.3) C2 (2) C2 (10) Ci (5) Ez (12) Ci (34) Co (5) Sz (12) C1 (5) C2 (3) Ci (5) Co (12) StSb.ZO) S2S10) Sz (5) Ci (12) Co (104) 02 (1.12,36,39,105) CQ (10) C2 (1) Gi (2.3) C2 {3) Ci (10) Table 3 Content Setting the initial state Getting intermediate, result Check intermediate result Reset register reset Receiving a checkout Checking the result and receiving the object code Write the first address TFN in 1PZU2 and IZuz iust. ex. status Pr05. PrP12. BK15 Read 1PZU2 Formation ai Census PrP12-Pr05 Reading 2PRUS and writing Pr05 . Getting the result Issuance of the result Installation Ref. status PRU and record counter code on the RgPZU Read 2PZUZZ and write RgPU Continued tabl, 3 That is 4 Table 5 Table b Table 7 Table 8 T a b faces 9 Table 10 2 (Horses figl ( GLU) J ct otfCfj AIB 5 65 Counted Direction (Cif) FIG. B FIG. 9 113 t 115 9u.lO X ShFSh - / I ti .go 125 M FIG. eleven Fzg 1Z CoA Phew