SU1704140A1 - Time test signal selector - Google Patents

Abstract

The invention relates to chronometric systems, in particular, selectors of time verification signals transmitted by a state time and frequency reference service. The purpose of the invention is to increase the reliability of selection of time verification signals and reduce the coupling time under conditions of high noise level by making it possible to extract a synchronized signal from different signals. view sequences of input pulses. The selector of time verification signals contains detector 1. elements are EXCLUSIVE OR 2 and 3. generator of 4 pulses, first 5 and second 6 counters, element OR 7, elements 8 and 9 DELAY, triggers 10-16, switch 17 pulses, analyzer 18 programs, elements Both 19.20 and 21, the elements are NOT 22 and 23 and the output driver 24. The selector of the time check signals allows the selection of a synchronized signal from various sequences of input pulses, which increases the reception time of the clock signal. 2 Il.

Description

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The invention relates to electronic timekeeping, in particular to time selector signal selectors, intended for automatic assignment of a time scale generated by a chronometric device, to a time scale generated by a national time and frequency standard (AGFC) and transmitted by radio stations in the form of characteristic points of reference signals of time.

The purpose of the invention is to increase the reliability of the selection of time verification signals and reduce the time of coupling in conditions of a high level of interference due to the possibility of separating a synchronized signal from various sequences of input pulses.

FIG. 1 shows a structural electrical circuit of a time check signal selector: FIG. 2 - time diagrams that show his work.

The time selector signal selector contains detector 1. elements EXCLUSIVE OR 2 and 3, pulse generator A, first 5 and second 6 pulse counters, element OR 7, first 8 and second 9 delay elements, first 10, second 11. third 12, fourth 13 , fifth 14, sixth 15 and seventh 16 triggers, switch 17 of pulses, analyzer 18 of the type of sequences of input pulses, first 19, second 20 and third 21 elements And, first 22 and second 23 elements NOT and shaper 24 of the output signal.

The time selector signal selector works as follows.

If there are no time verification signals in the radio channel at the input of the detector 1, the signal is absent, the trigger 11 is in such a state that a high level of potential from the trigger 15 arrives at the input of element I 19, and you set the input pulse from the counter to this state 6 through the former 24.

From the output of the element And 19 to the second input of the element And 20 comes a high potential level, at the first input of the element And 20 there is also a high level coming from trigger 12. which is set to this state by pulses from the generator of 4 pulses. From the output of the element AND 20, a high potential level through the element OR 7 is fed to the inputs of the installation of zero counters 5 and 6 and the generator of 4 pulses, which in this case are in the initial state.

When a time verification signal arrives at the input of the detector 1, a sequence of video pulses is formed at its output (Fig. 2 a, b). The leading edge of the first pulse trigger 11 is transferred to a state in which a low potential level is established at its output.

Thus, a high potential level is removed from the second input of element AND 19, which results in the removal of a high potential level only from the second input of element AND 20 and the input. Setting zero, generator 4

0 pulses and counters 5 and 6. At the outputs of the generator of 4 pulses, pulse sequences begin to form (Fig. 2c, d), similar to the second impulses of type Ai. transmitted by the GHF service.

5 and at the second output, pulses begin to form (Fig. 2e), similar to minute pulses, but with a 1c following period. One of the pulses from the third or fourth outputs of the generator 4 pulses through the switch 17 is fed to the first input of the EXCLUSIVE OR 2 element, the second input of which receives a pulse sequence from detector 1. If the first input of the ISK-5 element has a pulse coming from switch 17, does not coincide with the pulse at the second input coming from the output of detector 1, then a high level potential is formed at the output, which through

0, the delay element 8 arrives at the first input of the trigger 11, sets it to a state in which a high potential level is formed at its output and through the elements AND 19 and 20 and the element OR 7

5 is fed to the inputs. Setting the zero of the counters 5 and b and the generator of the 4 pulses, sets them to their initial state. At the same time, the pulse present at the first input of the EXCLUSIVE OR 2 element is poured into the memory of the analyzer 18. When the pulses at the inputs of the EXCLUSIVE OR 2 element repeat, the described process is repeated and the second one is recorded in the program analyzer 18 memory.

5 pulse, and in the counter 5, the accumulation of information does not occur, since with each successive pulse mismatch it is reset to the initial state and at the first input of the analyzer 18 connected

0 with the output of the older, for example, second bit of counter 5, there is no signal. At the output of the analyzer 18, a signal appears that sets the trigger 13 to another state, in which the switch 17 switches the output of another type of signal coming from the generator of 4 pulses.

If the signal at the first input of the element EXCLUSIVE OR 2. coming from the switch 17, coincides with the signal at the second output coming from the detector 1,

then the high potential level is not formed at the output and the trigger 11 remains in the state in which the inputs of the generator zero setting 4 pulses and counters 5 and b present a low level potential, and the pulse generator 4 continues to generate a pulse sequence of signals (Fig. 2c). , d) The pulses generated by the generator 4 pulses through the switch 17 are fed to the counter 5. When the pulses are successively coincided at the inputs of the EXCLUSIVE OR 2 element, the pulses from the pulse generator 4 are recorded in the counter 5. After the second pulse from counter 5 to the first input of the analyzer 18, a high level potential arrives, signaling the correctly selected type of pulses from the generator of 4 pulses corresponding to the received channel pulses transmitted by the GOLF at a given time.

After, for example, the sixth pulse, the counter 5 is filled and a high potential level is formed at its output, setting trigger 15 to a state in which a high potential level, coming from its output to element 19, also removes the signal from element EXCLUSIVE OR 2 through the element And 19 at the output Setting zero generator 4 pulses and counters 5 and b no longer arrive.

In order to exclude the possibility of resetting the counters 5 and 6 and the pulse generator 4 by interference present in the communication channel from the element 20, through which this installation occurs, the potential of the high level is removed for the time determined by the end of the pulse studied and the beginning of the next expected pulse in the communication channel. The high potential level from the first input element And 20 is removed by the trigger 12, which is controlled by the pulse generator 4. After filling the counter 5, the time selector signal selector is considered to be tied to the second scale transmitted by the AHFC on the communication channel.

At the first input of the element 21, a high potential level is received from the element NOT 23 controlled by trigger 15, and to the third input is a high potential from trigger 10, but only if its first input does not receive a pulse from the element EXCLUSIVE OR 3, to the first input of which, every second, a pulse similar to a minute mark (FIG. 2 e) is transmitted from the generator of 4 pulses transmitted over the communication channel by the GOLF service. and on the second

input signals from the detector output 1.

Thus, at the first input of the trigger 10, a signal removing a high potential level from its output will be absent only if the output of the minute mark is present at the output of the detector 1. To the second input of the element And 21 at the end of every second from the first output

0 generator 4 pulses a pulse is received, ending with the leading edge of the next second. At this moment, at the output of the element 21, a signal is generated that sets the trigger 16 to such

5, the state in which the high level potential is removed from its output and through the OR element 7 enters the inputs Setting the zero of the counters 5 and 6, sets them to the initial state. Simultaneously, the signal from the trigger 16 is fed to the first input

trigger 14 and sets at its output

low potential coming

at the entrance Resolution of the counter account

Counters 5 and 6 are included in the follower5 but their total filling is designed for 59 pulses. The moment of the complete filling of the counters 5 and 6 corresponds to the leading edge of the next minute mark transmitted over the communication channel by the GOLF service. The output signal from the counter 6 is fed to the output signal generator 24, the output of which is the output of the time check signal selector and sets the triggers 14 and 15 to the initial state, and

5 is also counter 6, which will correspond to the initial state of the selector of the time test signals and its readiness for the new reception of the GOLF signals. The initial state of the trigger 16 and the driver 24

0 is driven by a signal from an inverter 22 controlled by a clock frequency. The duration of the selector output is determined by the period of the choke frequency.

Claims (1)

5 claims The selector of signals of check of time containing consistently connected first element EXCLUSIVE OR. pe delay element and first 0 trigger, the output of which is connected to the first input of the first element AND, to the second input of which the first output of the pulse generator is connected, the second output of which is connected to the first input of the first element 5 EXCLUSIVE OR, and the serially connected second element EXCLUSIVE OR, the second delay element and the second a trigger whose output is connected to the first input of the second element AND, the first input of the second element EXCLUSIVE OR is connected to the second input of the first trigger and to the input of the first pulse counter, and the second inputs of the first The second and second elements EXCLUSIVE OR and the second input of the second trigger are connected to the detector output, the first and second additional outputs of the pulse generator are connected, with the corresponding inputs of the third trigger, the first output of the first counter of the pulses is connected to the first input of the fourth trigger, and the second output of the first the pulse counter is connected to the counting input of the second pulse counter, to the Permission input of which the output of the first flip-flop is connected, the first input of which is connected via the OR element to the inputs Ul, the pulse generator, the first and second pulse counters, and the second input of the fourth and fifth triggers are interconnected, as well as the sixth trigger and the third element I. distinguished by. that, in order to increase the reliability of the selection of time verification signals and reduce the time of interference in high-noise conditions by ensuring the selection of a synchronized signal from various sequences of input pulses, the analyzer of the type of sequences of input pulses, the seventh trigger, pulse switch, driver you 0 0 five 0 five the current signal and the inverters, with the output of the third trigger and the output of the second element AND through the third element AND are connected to the second input of the element OR, the third and fourth outputs of the pulse generator through the pulse switch are connected to the first input of the second element EXCLUSIVE OR, and to the first the input of the analyzer of the sequence of input pulses, to the second input of which an additional output of the first pulse counter is connected, and the output of the analyzer of the type of sequence of input pulses through the sixth trigger soy It is connected to the control input of the pulse switch, the clock input of the pulse generator is connected to the corresponding input of the detector and to the input of the first inverter, the output of which is connected to the control input of the output signal generator and to the first input of the seventh trigger, the second input of which is connected to the output of the first And element, to the third input of which the output of the second inverter is connected, the input of which and the second input of the second element I are connected to the output of the fourth trigger, the output of the seventh trigger is connected to the first input of the element SLT. and the output of the second pulse counter is connected to the input of the output signal generator, the output of which is connected to the second input of the fifth trigger.  Yav "g 1 p K - ft . CRASH n .... PL. l .. n .....