SU1700758A2 - Pulse interference protection device - Google Patents

Abstract

The invention relates to radio engineering and can be used in devices for transmitting discrete information. The aim of the invention is to increase the noise immunity by forming output pulses that are equal in duration to the input pulses. The goal is to introduce a counter 1, an AND-NE 8 element, an OR-NOT 14 element, a D-flip-flop 9, a pulse shaper 3, and a delay block 4 that restores the duration of the pulse sequence from the first output of the device to the duration of the input pulses. A pulse train with a restored duration is formed at the second output of the device with a delay equal to the minimum duration of the input pulses. 1 il.

Description

The invention relates to radio engineering, can be used in various devices for transmitting discrete information and is an improvement of the known device according to ed. St. No. 1095427.

The purpose of the invention is to increase noise immunity due to the formation of output pulses, duration K) equal to the input.

The drawing shows a structural electrical diagram of the proposed device,

The device comprises a second binary counter 1, inverter 2, pulse shaper 3, delay unit 4, first additional coincidence element 5, second coincidence element 6, third additional coincidence element 7, AND-NOT element 8, · D- trigger 10, second additional match element 11, first match element 12, first binary counter 13, OR-NOT 14. 25

The device operates as follows.

The operation of the device begins with the control of the duration of the input pulse. For example, when the first pulse of the input sequence arrives at 15 input at the output of the coincidence element (AND-NOT element) 5, level 0 is set, and at the output of the coincidence element 11 35 (OR-NOT element), level 1 is set and counter 13 starts counting the clock pulses with a period t ₀ .

Element 12 matches SOS- shaking the counter 13, arising after bills clock impulses ^P DANI to ) (1)

where is the minimum duration of the input pulses.

If t _MMH , match element 7 (NAND) after a time t _MnH gives an impulse. This pulse counter 14 writes the inverse code number n _min, and resets the trigger counter 10. When this coincidence element 5 is closed and the counter 13 is reset ^{level 0} "from the output matching element 11. 55

At the end of the input pulse, the device begins to control the duration of the pause t _n between pulses. The element of coincidence AND-NOT 6 opens and at the input of the reset counter 13 is set to level 1, allowing the count of clock pulses. The coincidence element AND-NOT 7 captures the state of the counter 13 that occurs after counting η clock pulses tflH ^{П П П} ё 'where t is the nominal duration of the pause between pulses.

If t _n >, the output pulse of the coincidence element 7 switches to “0” trigger 10 and resets the counter 13. An output is generated at the output of the AND-NOT 8 element, the duration of which is determined by the difference:

& t ₍ = t _t - (3)

Block 4 provides a delay of the trailing edge of the input pulse for a time longer than the switching time of the trigger 9 and the element ORINE 14, which is necessary to eliminate the gap in the output pulse of the element.; OR NOT 14 ,.

On the trailing edge of the input pulse, the driver 3 generates a pulse "switching D-trigger 9 in 1". Counter 14 begins to count the clock PULSES. AND AFTER TIME t _Wv , _H = gives an output pulse that sets trigger 9 to O. Thus, the pulse duration at zero, the output of trigger 9 is also equal to the pulse duration at the output of the OR-NOT 14 element and, accordingly, at the output 16 is equal to the total duration of the pulses at the inputs of the element OR — NOT 17, i.e. t Ί '£ in ”·

The pulse at the output 16 is delayed relative to the input pulse for the time C * and "·

When a pulse of duration shorter than the minimum t s t is received, the counter 13 does not have time to count ^p min clock pulses. Therefore, a pulse at the output 17 is not formed, trigger 10 remains at 1 and the counter '13 is reset at the end of the pulse * Thus, the device suppresses the noise False pulse. If the impulse noise arrives repeatedly, then the process is repeated many times. At the outputs of the device pulses due to interference There is no false pulse.

Interference Impact loss is determined by the duration of the pause $ t when the condition t _n with t is fulfilled. Elements 7 and 12 coincidence in this case form the output pulses. The input pulse coming after this pause to output 16 does not pass, since trigger 10 remains in state 0 and level 0 is set at the counter reset inputs. After this pulse ends, counter 13 starts monitoring the pause duration and if t _n > t _nHj 15 trigger 10 switches to 1 and the device, upon receipt of the next input pulse, starts to work in the pulse width control mode. Thus, the device returns to its original state after interference. Impulse loss.

Claims (1)

Claim Device for protection against impulse 25 interference according to auto-sn No. 1095427, including the fact that, in order to increase the noise immunity due to the formation of output pulses, equal in duration to the input pulses, a second binary counter, a delay unit, a pulse shaper, a D-trigger, and -NOT element OR-. NOT, and the outputs of the first binary counter are connected to the bit inputs of the second binary counter, the clock input of which is connected to the clock input of the first binary counter, and the output is connected to the first input of the D-trigger, the first output of which is connected to the first input of the IPI-NOT element, and the second output - with the reset input of the second binary counter, the inverter input is connected to the input of the pulse shaper and through the delay unit to the first input of the AND-HE element, the output of which is connected to the second input of the OR-HE element, the output of which is second By the direct output of the device, the output of the pulse shaper is connected to the second input of the D-trigger, the third input of which is connected to the inverse output of the counting trigger connected to the second input of the AND-NOT element.