SU1688473A1 - Analog-to-digital converter with error correction - Google Patents

Description

(21) 4616751/24

(22) 12/05/88

(46) 10/30/91. Bul No. 40

(71) Institute of Cybernetics im.V.M.Glushkova

(72) I.V.Samus

(53) 681.325 (088.8) (56) Stakhov A.I. A seventeen-bit self-correcting ADC. Instruments and control systems, 1986, K 1, p. 18.

USSR author's certificate 1356223, cl. H 03 M 1/10, 1985. (prototype.

(54) ANALOG-DIGITAL CONVERTER WITH CORRECTION OF ERROR

(57) The invention relates to computing. The invention improves accuracy. This is achieved by introducing an analog-to-digital converter.

13 code voltage, summation blocks 4, clock generator 6. key block 7, counter 9, subtractor 10, memory 11, correction search block 12, source 13 reference voltages, an

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oo oo

four

with

.one

the key 14, the digital switch 15 and the register 16. This reduces the number of verified points of the conversion range and reduces

The invention relates to computing and can be used as a stand-alone module for performing analog-to-digital conversion with high accuracy.

The purpose of the invention is to improve accuracy.

Fig. 1 shows a functional diagram of an analog-to-digital converter: Fig. 2 shows a functional diagram of a RAM block; FIG. 3 shows a functional block of the search for amendments; Fig. 4 is a functional diagram of a source of reference voltages; in fig. 5 - 7 are the timing diagrams of the operation of the RAM unit, the correction search block, the source of reference voltages, respectively.

The analog-digital converter with error correction contains a pulse former 1, a delay element 2, a code-voltage converter 3, a summation block 4, a voltage-code converter 5, a clock generator 6, a block of 7 keys, a RAM block 8, a counter 9 , subtractive device 10, memory 11, correction search block 12, source 13 of reference voltages analog key 14, digital switch 15, register 16, element 17.

The memory unit (FIG. 2) contains a counter 18, an element of AND 19. an element of AND 20, a register 21–23, an element OR 24, a register 25 and a block 26 of comparison.

The correction search block (FIG. 3) contains a delay element 27, elements 28 and 29, a memory 30, a decoder 31, a reversible counter 32, a register 33. a trigger 34 and a digital switch 35.

The source of reference voltages (FIG. 4) contains an OR 36 element, a reference voltage source 37, a trigger 38, a counter 39, a digital-to-analog converter 40, an AND 41 element, a voltage divider 42, a counter 43,

dynamic error, as well as correct non-linearity and non-monotonic errors. 3 hp ff, 7 ill.

0

five

0

0

five

five

five

register 44, switch 45, multiplier 46.

The analog-digital converter operates in two modes: in control mode and in conversion mode with result correction. In the first mode, the verification of well-defined points of the conversion range of the converter 5 and the calculation of corrections are carried out. In the second mode, the input value is converted, the corresponding correction is determined, and the result of the conversion is corrected. In this case, if there is non-monotony of the transfer characteristic, i.e. the same code at the output of the voltage-code converter corresponds to different input values, then only corrections corresponding to the given point of the range are searched.

At the initial moment, the cells of the memory device 11 and the memory device 30 are reset.

With the arrival of a single pulse, the start of the counter 9 is zeroed, the output of the source 13 is set to the zero level of the analog signal and the zero code on the digital outputs. The zero potential at the output of the counter 9 determines the control mode. At the same time, the output of source 13 via analog switch 14 is connected to the first input of block 4. Since the control output of block 12 is set to a high level, since no corrections are searched for, the outputs of block 7 are set to zero in all bits, which corresponds to zero voltage. The output of converter 3. Thus, a reference voltage is applied to the third input of converter 5, the first conversion being equal to zero. At the same time, according to the Start signal, the driver 1 generates a single impulse, ON | the leading edge of which the converter 5S is launched on the second address outputs of block 8 is set to zero

The clock pulses from the output of the clock generator 6 to the second input of the converter 5 produce a one-by-one equilibration of the input value, and a digital code is formed at the information outputs of the converter 5, corresponding to the input voltage taking into account the error. At the same time, in block 8, the address of the amendment is determined. Upon completion of the conversion, the output pulse of the converter 5 is formed by a zero pulse, on the leading edge of which the result is entered in block 8 and set at its first outputs. At the address outputs of block 12, an additional address of the correction is formed, which is equal to the number of occurrences of this conversion result in the control mode; it is in the input control conversion mode, in this case 00 ... 01.

Thus, on the first and second address inputs of the storage device 11, the primary and secondary addresses of the correction are set, respectively, and on its information inputs, the correction code is equal to

N,

l;

where id; 1J

 N. - N AI oi)

Hi

N

Oi

correction code of the i-th point of the range;

reference voltage conversion result code; code of the reference voltage corresponding to the i-th point

since the result of the conversion is set on the second group of inputs of the subtractor 10, and the code corresponding to the reference voltage from the outputs of the source 13 through the digital switch 15 is set on the first group of inputs.

After a time determined by delay element 27 of block 12, during a zero pulse at the ready output of converter 5, this correction value is recorded in memory 11. At the end of the zero pulse, the following reference voltage value and the corresponding code are set at the reference voltage source. The contents of counter 9 is increased by one and after the time determined by delay element 2, driver 1 is restarted. Verification is performed at the next point. The result

0

five

The calculations in the control mode are not written to register 16, so there is a potential at the second input of element 17. In this way, all the set points are rotated.

In the event that during the verification process, due to the non-monotonicity of the transfer characteristic of the converter 5, the result of the reference voltage conversion obtained earlier, i.e. at this address, the amendment has already been determined, the additional address n at the output of block 12 is incremented by one, and the value of the amendment is recorded in a free cell. When all M points are verified, the logical unit level is set at the output of counter 9. Thereby the device is foam sized.

In this case, the analog output of the source 13 is set to zero, and its digital outputs zero code. The digital switch 15 is connected to the first inputs of the subtractor 10, the outputs of the storage device 11. In this case, it is switched to the read mode. The analog switch 14 connects the input voltage to the first input of the summation circuit, and with the arrival of the next triggering pulse from the output of the driver 1, the input voltage is converted.

Upon completion of the conversion on the leading edge of the pulse coming from the ready output of the voltage converter-code 5. The conversion result is recorded in block 8 and set at the outputs of the first group of block 8, at the outputs of the second group of which the main address of the correction is already set, corresponding to the result

transform. At this address. On

the outputs of the storage device 11 is given a correction code, which, entering the inputs of the first group of inputs of the subtractor TO, via a digital

switch 15 is subtracted from the result code. Wherein

N

TO.

 N ... - N.,

fli d

where is II,

- adjusted result

transform.

This code is on the leading edge of the next trigger pulse that forms the output of driver 1,

n register is entered 16. Thus, M conversions are performed. After that, the output of the counter 9 is reset to zero potential, and the device is transferred to the control mode, which, in turn, is replaced by the conversion mode, and so on until the first input of the Shaper 1 generator of the Stop signal turns off at the first input. the formation of trigger pulses.

If during the conversion process a result is obtained that corresponds to several amendment values, as evidenced by the additional address code at the outputs of block 12, exceeding 00 ... 01, a corresponding correction is searched. In this case, a zero level is established at the control output of the block 12, which blocks the recording of the conversion result to the register 16, the flow of code combinations through the block 7 to the inputs of the converter 3, which drives the negative voltage, is permitted

ti

and it is prohibited to change the code on

first and second pmupdas of R.

The amendment is searched as follows.

The correction code selected at the main address, which does not change, and the sub address, which decreases by one conversion in the search process, goes to the subtraction device 10 for correction. The corrected result goes to the inputs of the code-voltage converter 3. The converted analog signal of the negative polarity corresponding to the corrected code is fed to the second input of block 4, which performs its summation with the input voltage. The resulting analog difference with the arrival of the next trigger pulse is converted by converter 5 and stored in block 8. At the same time, the additional address is reduced by one on the leading edge of the conversion end pulse of the converter forming at the ready output of converter 5. transformer 3, corresponding to

five

0

five

0

five

0

five

0

result of the new value of the amendment. Difference codes are compared in block 8 and the sub-address of the amendment corresponding to the smallest difference is stored in block 12. These operations are performed for all corrections belonging to this primary address.

The amendment search is terminated, and the amendment is taken as the true one, corresponding to the minimum difference. At the control output of block 12, the level of the logical unit is set, and the result corrected by the value of the found correction is written to the leading edge of the next triggering pulse in the 1G register) {Since the number of transformations counted by counter 9 is equal to II, the counter is also searched for the correction. ) is not blocked; the more non-monotonous points of the transfer characteristic, the more often is the transition to a hard control.

PaOiia of the block I online memory in the conversion and control modes illustrates the HP League timing charts,) And for the example, select the number of bits of the analog-to-digital converter, and consider the number of city-bits m 3. If no correction is performed then the logical unit is present on the first block flow. At the same time, the passage of pulses through elements 19 and 20 is permitted. Recording of the result in register 22, but the operation of register 23 and the bar 26 is prohibited. With the arrival of the triggering pulse front at the first input of element 20, register 21 is zeroed. At the output of element 24, a logical zero signal is generated. Thereby, the counter 18 is reset and a logical unit signal is set at its output. With the beginning of the conversion on the falling edge of the clock pulses coming from the second input of the element 19 to the building input of the register 21, information about the outputs of the converter 5 is written into the parallel code. For example, in Fig. 5, the code 01011 is received as a result of the conversion, It is noteworthy that the first cycle in pei .IOTP 21 is 00000, and by ropoMV is 01000. In this case, the output of element 24 sets a logical unit signal and resolves to slave i of counter 18, By

The front dodo of the third Ti Tiu oro pulse in counter 18 is written to one, and by decay to register 21 it is the code of the SLLI. On the leading edge of the fourth pulse, the contents of counter 10 are two, and on a decay, code 01010 is written to register 21. On the leading edge, the contents of the counter are purely three, and the output level is set at the output level, which blocks the passage of clock pulses through element 19 Therefore, the contents of register 21 remain unchanged, although after the fifth pulse at its inputs the code is 01011, i.e. the main address of the amendment determines only the n-high bytes of the code, in this case three, starting with the first one included. Upon termination of the prescription on the leading edge of the pulse arriving at the gate input of the register 22, the conversion result code is entered about it. Figure 5 shows the process of generating the main address of the correction for the conversion result code 11011. In this case, the main address is 11000.

If a correction search is performed, a zero level is set at the first input of the block. In this case, the passage of pulses through elements 19 and 20 is prohibited, and consequently, a change in the contents of registers 21 and 22, in which the main address and the result of converting a range point in the non-monotonic region are stored. At the same time, the operation of register 23 and block 26 is permitted, and in register 25 in parallel code, code 11 ... 1 is entered. 1. After the first conversion of the difference between the input and corrected value, the result on the front of the end of the conversion pulse input to the gate input 23, is written to this register and is compared by block 26 with the contents of register 25. If register code 23 is less than content register 25, and this is always done at the first conversion, then the leading edge of a single pulse is formed at the output of block 26. To the second, the contents of register 23 are rewritten to register 25, and in block 12, the additional address of the amendment corresponding to this difference is rewritten to register 33. Because

Jq ii 20 25

30 OE 40 45 50

five

After the search is completed in register 2rj, the code of the smallest difference appears, p in register 33 of block 12 - the corresponding one is added to address of the amendment.

The operation of the correction search block is illustrated in the time diagrams of FIG. At the same time, the number of RPMs and PJs n and the number of bits to be taken into account m are also equal to 5, t i.

ii control mode on the perg Rochod element 27 of the delay level of the logical zero, which prevents its operation. The same level prohibits the operation of the decoder 31 and the pa trigger. Therefore, at the output of trigger 3, the level of logical units. Thus, the passage of the nvny ibCO through the element 29 is blocked and the passage through the tape 28 is permitted. At the initial moment, all the cells of the memory device 30 are cleared. Upon completion of the conversion of the reference voltage corresponding to a given point of the range, the main address travels from the second outputs of block 8 to the address inputs of the primary device 30. The front end of the conversion end pulse to the second input of delay element 7 and the first input of element 28, and the counter 32 in the parallel code enters the code from the outputs of the storage device 30. Through the time determined by the delay element 27, at its output also generates a zero pulse, on the leading edge of which it contains The counter is incremented by one, and in the rear, the code from the outputs of counter 32 is recorded and stored (its device is 30. By the same Front, the correction code is also recorded in memory 11. At the same time, the output level of the counter 32 is high, its outputs through digital switch 35 are connected to the outputs of the block, thereby forming the code of the additional address of the amendment.If in the process of verification, the code of the main address is encountered a second time, the contents of the counter 32 are incremented and equal to two. This number is recorded in a memory 30. Similarly, I1688473

A new process occurs at the jth occurrence of this address.

p h with

In the conversion by the formed main address, the information is selected from the storage device 30 and is recorded in account 32. At the same time, the operation of the delay delay 27 is prohibited and the operation of the decoder 31 and the trigger 34 is enabled. If the code at the output of the storage device 30 exceeds 00. ..01, for example, for FIG. 6, it is equal to 011, then the zero state of the decoder 31 is recorded by the impedance end of the conversion to the trigger 34. At the output of the trigger 34, the value of the logical zero is set. At the same time, the passage of pulses through element 28 is blocked and passage through element 29 is allowed. After the first conversion on the pulse front of the end of the conversion, the contents of the counter decrease by one. Thereby, an additional address of the next amendment is set at the output of the digital switch 35. 6, this is 010. Let the correction with this additional address correspond to the minimum difference. Then, with the arrival of the leading edge of the pulse at the gate input of register 33, this code is entered into this register. When ace corrections are checked, i.e. corrections with additional addresses 011, 010. 001, at the output of the overflow of the counter 32 A zero pulse is formed. Thus, trigger 34 is reset, the search for corrections is stopped, and a digital switch connects the outputs of register 33 to the output of the block, i.e. for correction, the optimal correction is selected from the storage device 11. The conversion process continues. The source of reference voltages operates in accordance with the timing diagrams shown in Lig.7. If the number of bits and the number of bits to be counted, then the counter 39 is two-bit, the digital-to-analog converter 40 is three bits, the switch 45, the divider 42, and the register 44 are three bits (n-m + 1 3). the multiplier is 46 five-bit, and the size of the counter 43 is determined by the number K ent Јlog. (n-m) J +1, in this case K 2. -

five

0

five

The process of generating a reference voltage is illustrated in the table. Moreover, for consistency, the quantum value is 1 mV. and the weights of bits are 4, I, 16 mV, respectively.

With the arrival of the impulse Start trigger 38, the counters 39 and 43 are set to the zero state, and the register 44 enters the code 00 ... 01, in this case 001. At the output of the Sch1 analog converter, the voltage is set to zero, and at the output of the multiplier 46 - zero code, since 001.000 00000, the first transformation is performed, after which the impulse of the conversion end arriving at the counting input of counter 39 ends, its content is increased by one. In this case, the low-order bit of the digital converter about converter 40 with a weight of 4 mV is switched on. Since with the code at the outputs of the counter 43.00, the output of the switch 45 is connected to the output of the divider with the maximum division factor, in this case 4s at its output a voltage of 1 mV, and the output of the multiplier code 001.001 00001. A voltage of 2 mV and 3 mV is also generated. In this case, when the number of transformations gives a number, in this case after the fourth conversion, 5 the counter 39 is zeroed out, and at its output of the overflow a zero overflow pulse is formed, on the leading edge of which the trigger one is entered at the trigger 38, and at the output of the AND 4 1 sets the voltage of the logical unit. The most significant bit of the digital-to-analog converter is turned on, and the state of register 44 and counter 43 does not change, i.e. the division factor and the multiplication factor remain the same.

I

In this case, the output of the switch 45 will be a voltage of 16: 4 4 mV, and the output of the multiplier is code 001.100 00100. When the points corresponding to the reference voltage of 20: 4 5 mV 24: 4 6 mV and 28: 4 7 mV are verified codes 00101, 00110, 00111, a zero pulse is generated at the output of the overflow of the counter 39 nov, and the counter 39 is zeroed. In this case, as the first in y. ode element And 41 - logical unit, at its output

0

0

45

50

five

I 3

a difference 1.0 is formed, by which the contents of counter 43 are incremented by one, and the code in register 44 is shifted to the left, with entry into the freed gazr d zero. The output of the switch 45 is connected to the output of the divider 42 with a division factor of 2 and the output of the switch 45 is set to voltage mV, the output of the multiplier is a voltage of 16: 2 8 mV. At the output of the multiplier, the code 010.100 01000 is set.

Thus, all M points are turned, and in this case twelve (Fig. 7 and a table). This number is counted by the counter 9. When all points are verified, a logical unit is set at its output, and therefore, at the first input of element 36. The same happens at the output of element 36. In this case, the trigger 38, the counters 39 and 43 are zeroed and the output of the switch 45 is set to a logic zero, and the output of the multiplier 46 is a zero code.

V about p

Claims (4)

1. Analog-to-digital converter with an error correction, containing the element I, a storage device, a voltage-code converter, the readiness output of which is connected to the input of the delay element whose output is connected to the first input of the pulse shaper, the output of which is connected to the first input of the operational memory block ti, the group of inputs of which is connected to the corresponding information outputs of the voltage-code converter, which is due to the fact that, for the purpose of increasing the accuracy, a code-voltage converter is inserted into it voltage, summing unit, a clock generator, the key unit, the counter, subtractor, the search unit corrections, a source of reference voltages, an analog key, a digital switch and a register, whose outputs are an output bus, and a building input is connected to an output 16 ment And, the first input of which the input is connected to the control to the output of the pulse former, the output of the RAM, the second and third inputs of which are the control output are connected to the third, respectively, by buses. The element is stopped by the input element I. the fourth inlet is started, the output of the driver of the RAM and control unit ten 3473 | 4 The coil is connected to the first input of the voltage-code converter, the second input of which and the second input of the RAM unit are combined and connected to the output of the clock generator, the ready output of the voltage-converter code is connected to the third input of the RAM unit, the first input the correction search block, the first input of the source of the reference voltages and the counting input of the counter, the setup input of which is combined with the second input of the source of the reference voltages - is the Start bus, the output of the counter is connected to the second input m amendments search block, the second input of AND, adjusting input of the memory device 20 control input of the digital switch, the third input of the reference voltage source and the first input of the analog switch, a second input of which is the input bus, the output is connected to the first input unit sum15 25 0 five 0 five 0 the third input is connected to the analog output of the source of the reference voltage, the digital outputs of which are connected respectively to the inputs of the first group of inputs of the digital switch, the inputs of the second group of inputs of which are connected to the corresponding outputs of the storage device, the outputs are connected to the inputs of the first group of inputs of the subtractor, the inputs of the second group of inputs of which are respectively connected to the outputs of the first group of outputs of the RAM block, and the outputs are connected to the corresponding informational inputs of the key block, informational and register inputs and informational inputs of the storage device, the first address inputs of which are combined respectively with the inputs of the group of inputs of the correction search block and connected to the corresponding outputs of the second group of outputs of the RAM, the second address inputs and the strobe the input of the storage device is connected respectively to the address outputs and the gating output of the search block of amendments, the third Lb16 The key input unit, the outputs of which are connected to the corresponding inputs of the code-voltage converter, the output of which is connected to the second input of the summation unit, the output of which is connected to the third input of the voltage-code converter. 2. The converter according to claim 1, T is characterized by the fact that the RAM block is made on two AND elements, an OR element, four registers, a comparison block and a counter, the installation input of which is connected to the output of the OR element. the output of the counter is connected to the first input of the first element AND, the counting input is combined with the second input of the first element AND and is the second input of the block whose first input is the first input of the second element AND, the third input of the first element AND is combined with the second input of the second element AND the installation input of the first register, the installation input of the comparison unit, the first gate input of the second register and is the fourth input of the unit, the output of the first element I is connected to the gate input of the third register, the installation input One of which is connected to the output of the second element AND, and the outputs are connected to the corresponding inputs of the OR element and are the second group of outputs of the memory block, and the information inputs of the third, first and fourth registers are respectively combined and are the inputs of the group of inputs of the block, the third input of which are the gate inputs of the first and fourth registers and the zero reset input, the outputs of the fourth register are connected respectively to the first information inputs of the comparison unit and the information inputs of the second The registry whose second gate input is connected to the output of the comparison unit, which is the control output of the unit, and the outputs of the second register are connected to the second information inputs of the comparison unit, the first group of outputs of the first register is combined with the installation output. the entrance of the first register. 3. The converter according to claim 1, in which i the correction block is executed on two Q 0 five 316 AND, memory, declaring, reversible counter, register, trigger, digital switch and delay element whose first input is combined with the decoder input and the first trigger input and is the second input of the block, the second input of the delay element is combined with the counting input of the trigger , the first input of the first element AND, the direct input of the second element AND is the first input of the block, the output of the delay element is connected to the gate input of the storage device, the first counting The reversing counter travels and is the gate output of the block, the input inputs of which are the memory address inputs, the information inputs of which are respectively combined with the information inputs of the register, the first information inputs of the digital switch and connected to the corresponding first outputs of the reverse counter, the memory outputs are connected to the corresponding information inputs of the reversible counter and information inputs of the decoder, the output of which is Connected to the information input of the trigger, the output of which is the control output of the block and connected to the second input of the first element AND and the inverse input of the second element AND, the output of which is connected to the second counting input of the reversing counter, the gate input of which is connected to the output of the first element AND, and the second output is to the second setup input of the trigger and the setup input of the digital switch, the outputs of which are the address outputs of the block, and the second information inputs are connected to the corresponding outputs of the reg Stra, strobnruyuschy input of which is the third input block. 4. The converter according to claim 1, T is characterized in that the source of reference voltages is made at the source of the reference voltage, the digital-analog converter, the voltage divider, the switch, the trigger, the counters, the element I, the register, the multiplier and the element OR, the first input of which is the third input of the source of reference voltages, 7 1 and the second input is the second input of the source of reference voltages, the output of the element OR is connected to the installation inputs of the first and second counters, the first input of the register and the installation input of the trigger, the output of which is connected to the first input of the AND element, the first input of the multiplier and the first input of the D / A converter the second input of which is connected to the output of the voltage source, and the third inputs are combined respectively with the second inputs of the multiplier and connected to the corresponding first outputs of the first counter, counting whose input is the first input of the reference source Reference Voltage Formation 8847318 5 and the second output is connected to the counting input of the trigger and the second input of the element I, the output of which is connected to the counting input of the second counter and the second input of the register, the outputs of which are connected respectively to the third inputs of the multiplier, the outputs of which are digital outputs 10 of the reference source analog output of which is the output of the switch, the first inputs of which are connected to the corresponding outputs of the second counter, and the second 15 outputs - to the corresponding outputs of the voltage divider, the input of which is connected to the output of the digital-to-analog converter. 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