SU1688127A1 - Multicomponent mixtures preparation process controller - Google Patents

Abstract

The invention relates to weighing technology and allows the device to become cheaper due to savings in computing power of the computer and to improve accuracy. The generator 1 outputs pulses to binary counter 2, which generates address codes by mass sensor 14. From the output of switch 5, the mass code of the selected mass sensor 14 is fed to the data input of the storage unit b. The operation of the device is controlled by a computer 23, having an interface 24 with buses 25-30, respectively, interrupt request, address, read memory, data, readiness and write to memory. In the device, hardware parameters are monitored by sensors 14 by setting a setpoint for each of which, in a block of 15 memories, compare current readings with settings in comparison element 17 and generate an interrupt signal with trigger 18 when the set value is reached. 1 il. (l c

Description

This invention relates to a weight measuring technique.

The purpose of the invention is to reduce the cost by saving computing power and improving accuracy.

The drawing shows a block diagram of the device.

The device contains a pulse generator 1, a binary counter 2, a decoder 3, an amplifier 4, a switch 5, a memory block 6, a Cy-to-binary binary code converter 7, a pulse shaper 8, an AND 9 element, an AND-HE element 10, a multiplexer 11, a selector 12 select information input unit, delay element 13, mass sensors 14, additional memory block 15 (setpoint memory), additional multiplexer 16, reference element 17, trigger 18, additional pulse generator 19, additional IS-NOT element 20, additional element And 21 extra a selector 22 (address), an electronic computer 23, having an interface 24 with buses 25-30, respectively, of interrupt request, address, read memory, data, readiness and write to memory.

As a computer 23, a microcomputer SM 1800 is used, having a standard AND 41 interface.

The device works as follows.

The pulse generator 1 generates pulses with a frequency of 1 kHz, which are fed to the input of binary counter 2, which forms

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the address codes of the sensors 14 mass. The address code is fed to the input of the decoder 3 and through the amplifier 4 to interrogate the switch 5, to the information inputs Di, .. Dn of which the signals of the mass sensors 14 are continuously received. From the output of switch 5, the mass code of the selected mass sensor 14 is fed to the data input of memory block 6. At the same time, the address code from the output of counter 2 is fed to the address input A 1 of multiplexer 11 and to the information input of multiplexer 16. When there is no signal to the information input unit from the interface 24, the output of the selector 12 receives the Forbidding signal to the first inputs of the AND-NOT elements 10 and 20. At the same time, from the outputs of these elements, permitting signals are received to the inputs of element I 21, from the output of which a signal arrives at the first input of element 9, permitting the passage of a recording pulse arriving at the second input of element 9 from the output shaper B pulses. From the output of element 9, a pulse simultaneously arrives at the input of the write permission of memory block 0, at the input of the read resolution of the memory of settings 15, at the input of the address sampling of the multiplexer 11, at the information input of the selector 12 and at the input of the pulse generator 19. At the same time, the address the inputs of the memory blocks b and 17 are received from the multiplexer 11; the address code m records the mass code of the selected batcher into the corresponding cell of the memory block 6 and reads the setting from the cell of the block 15. The signal received at the input DE of the address selector 12 prohibits access to the block information input from the interface 24 to the recording information in the memory unit 6. From the output of memory block 15, information from the corresponding cell is fed to input D. of comparison element 17, the input of which DI from output of switch 5 receives the value of actual weight. If the actual weight value has reached the setpoint value, then at the output of the comparison element 17, a signal is generated that arrives at the information input of the trigger 18. The latter is driven with a delay determined by the pulse former 19. This delay must exceed the transient time in the comparison element 17. From the output of the trigger 18, the interrupt signal is sent to the bus 25 of interface 24. After the interrupt signal is generated, the address generated by the counter 2 remains unchanged until the next oscillator 1 signal appears (approximately 0.5 ms ). During this time, the computer 23 can read the contents of counter 2, i.e. determine the number of the dispenser that set the interrupt. The circulation of the computer 23 is possible only after the termination of the weight recording pulse. At the same time, from the output of the element I 9 to the input DE of the selector 12 of the choice of the input

information is received, allowing the device to access the interface 24. The computer 23 is addressed when the otrigger 18 interrupt signal is present, when the settings are written into the settings memory 15 and

0 if it is necessary to read the current weight values from the memory block b.

When accessing the computer 23 from the interface 24 via the address bus 26 receives the sample code of the input information block A

5 of the selector 12, at the output of which a signal is generated that permits the execution of a read operation (RD) —the first input of an AND 10 element or write (WR) —the first input of an AND-NOT element 20, and outputs via element 13

0 delay signal readiness for interface 24 via bus 29.

When setting the settings to the block 15c of the interface 24, a write command is sent over the bus 30 to the second input of the element IS-NOT 20, from the stroke of which the write signal to the input of the block 15 is received. bus address 26 on the interface 24. At the same time, the signal from the output of the element IS-NOT 20 is fed to the first input of the element And 21, from the output of which the signal at the first input of the element 9 and prevents the recording of the current weight.

When reading the information about the current weight value from the interface 24, a read command is received via bus 27 to the second input of the NE-10 element, from whose output the read signal is fed to the input of memory block 6 and a multiplexer is sampled

0 11 addresses of the interrogated memory cell provided from the address 26 bus address of the interface 24 to the input А 2 of the multiplexer 11. From the output of the memory block 6 through the converter 7 and the multiplexer 16 information

5 current weight enters the bus 28 data interface 24.

At the same time, the signal from the output of the element AND-NOT 10 is fed to the second input of the element 21, from the output of which the signal

50 enters the first input of the element And 9 and prohibits the recording of the current weight.

To process the interrupt signal, the address 24 of the interface 24 must be set to an address that opens the selector 55 tor22 and a read command is issued on the bus 27 to the second input of the AND-NOT element 10. The output signal from the selector 22 through the multiplexer 16 transmits the metering code determined by the state counter 2, on the interface data bus 28. Next, this dispenser is disconnected programmatically.

Claims (1)

Formula of the Invention A multi-component mixture preparation process control device comprising an electronic computer with an interface having interrupt request, address, memory read, data, readiness and memory buses, weight sensors connected to the information inputs of the switch, output which is connected to the information input of the memory unit, the output of which is connected to the converter of the cyclic Gre to binary code, the pulse generator connected to the input of the binary counter and through the driver there are pulses - to one input of the I element, the output of which is connected to the first input of the address selection of the multiplexer, the recording input of the memory unit and the information input of the selector, the output of which is connected to the same input of the NAND element, and through the delay element to the readiness bus, the output of the binary counter is connected to the first address input of the multiplexer and through the decoder and amplifier to the address input of the switch, the second address input of the multiplexer and the address input of the selector are connected to the address bus, the output of the AND-NOT element is connected to the second the multiplexer address selection and the memory input of the memory block whose address input is connected to the multiplexer output, characterized in that, in order to reduce the cost by saving computational power and improving accuracy, an additional memory block is added to it, , comparison element, trigger, additional pulse shaper, additional AND-NOT and AND elements, and additional selector, with the address input of the additional memory block connected to the multiplexer output, information input - the data bus, the read control input — with the output of the I element, and the output — with one input of the comparison element, the other input of which is connected to the switch output, and the output — to the trigger information input, the output of which is connected to the interrupt request bus, one additional multiplexer information input connected to the output of a binary counter, another information input to the output of the cyclic code converter Gre to binary, and the output to the data bus; the address input of the additional selector is connected to the address bus, infor the custom one is with the output of the NAND element, and the output is with the sample input of the additional multiplexer and the trigger reset input, the synchronization input of which is connected to the output of the AND element, the additional input of the additional I element is not connected to the write bus in memory, the other input is with the selector output, and the output is with the write enable input of the additional memory block and one input of the additional AND element, the other input of which is connected to the output of the NAND element, and the output is connected to another input of the I. element