SU1686658A1 - Method for controlling voltage converter in a three-phase drive - Google Patents

Abstract

The invention relates to electrical engineering. The purpose of the invention is to reduce power consumption and increase operation stability by replacing a wide series of narrow current pulses of thyristor control with a single narrow pulse and eliminating the discontinuous current mode during a half-period of the network. In accordance with the proposed method, at the time of the end of the current in the switched phase, a reference signal is formed and compared with the reference signal for the duration of the dead time in the switched phase. The presence of current is monitored at the other two phases. If the current in the monitored phases is not zero, then at the moment of the equality of the indicated signals, a single narrow control current pulse is applied to the control transition of the thyristors of the switched phase. If the moment comes) when the current in the switched phases ends, and the comparison of the compared signals does not occur, then the formation of the reference signal stops at that moment, and the control transitions of the switched and phase thyristors, the voltage of which is lagging behind the voltage of the switched 120 ° a single narrow control current pulse is applied. 2 Il. to

Description

The invention relates to electrical engineering, in particular, to an electric drive with an asynchronous motor controlled by adjusting the magnitude of the voltage applied to the stator windings by means of a thyristor voltage converter.

The purpose of the invention is to reduce power consumption and increase work stability by replacing a wide series of narrow thyristor control current pulses with a single narrow pulse and

elimination of intermittent current mode for half network period.

FIG. 1 shows a block diagram of a device implementing a predictable method; on (lig. 2 - time diagrams explaining the method.

The device (Fig. 1) contains a flicker 1 synchronization consisting of a sensor 2 of conduction conductivity and a sensor 3 of the beginning and end of phase current, a phase control unit 4 consisting of a delay line 5, a block.6 of a pulse distributor, block

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SP, 00

7 control pulse formers containing three formers 8, thyristor voltage regulator of thyristors 9-14.

Fig, 2 presents: diagram 15

- voltage of phase A (UA) and current in phase A (1 l), diagram 16 - voltage of phase B (V) and current in phase B (1c). Diagram 17 - phase voltage C (Uc) and current in phase C (ic). chart 18

-signal on the first output of the synchronization unit 1, corresponding to the end of the current in one of the thyristors (IJBCl), diagram 19

-signal at the second output of the synchronization unit, corresponding to the onset of current by the corresponding thyristor (Uscz). Diagram 20 is a reference signal generated inside phase control unit 5 (Don) and a signal for the duration of a current-free pause (U3 g), diagrams 21-23 control signals of the corresponding thyristor pairs

(11BFU1, 1) BFU2, 1) BFUZ).

The method is implemented as follows.

At the end of the current in one of the phases, the synchronization unit forms a short pulse UBCI, which is fed to the input. Starting the phase control unit 5, inside which the reference signal Don, having a sawtooth shape, begins to form. In block 5, the signal Uon is compared with the signal Ouse. At the moment of equality of these signals, the block 5 at the output generates a pulse, which, through blocks 6 and 7, is applied to the control transitions of the corresponding pairs of matched thyristors 9-14. After switching on one of the thyristors, a signal appears at the second output of the synchronization unit, which enters the input Reset of unit 5 and resetting the sawtooth Don in it to the zero level. If the current in one of the phases until the equal time of the signals Uon and Uz j terminates, a signal is generated by the signal from the second output of the UBC2 synchronization block at the output of block 5, under which the signals from the output of block 6 trigger the corresponding thyristors 9-14. Unit 6 under the action of each signal from block 5 generates signals on its three outputs in succession. Under the action of the first

the signals from block 5 generate signals at the outputs of block 6, connected with phases A and B; under the action of the second signal from block 5, signals are formed at the outputs of block 6, connected with phases C and A, under the action of

The third signal from block 5 generates signals at the outputs of block 6, associated with phases B and C, etc. Shapers 8 form when entering their inputs signals from the outputs of block 6 on two outputs

single narrow pulses arriving at the oncoming thyristors of the corresponding phase.

Claims (1)

Claim Invention Control Method voltage in a three-phase electric drive, at which at the time of the end of the current in the switched phase they form a reference signal and compare it with the reference signal for the duration of the dead time in switching phase, characterized in that, in order to reduce power consumption and increase operation stability by replacing a wide series of narrow thyristor control current pulses by a single narrow pulse and eliminating the mode of intermittent currents over the half-period of the network, simultaneously control the presence of current in the other two phases, if the current in the controlled phases is not zero and the equality of the compared signals has come, a single narrow pulse of the control current is applied to the switching transition of the thyristors of the switched phase, if a moment has arrived when the current in the controlled phases finished, but the equality of the compared signals did not come, then the formation of the reference signal is also stopped and on the control transitions of the thyristors of the switched phase and phase, the voltage of which lags behind the voltage switched by 120 °, a narrow pulse of control current is applied. 2 DIAC, U1 d „Y Wn% -Y G8. M,  In In Jh r Oud; Vgn ,, n and nf "/ w," n n i r fuz. 2 . M, Oud; Vgn