SU1684808A2 - Device for multichannel recording and reading digital data signals - Google Patents

Abstract

The invention relates to instrument engineering and can be used to record and reproduce discrete information from communication channels to a magnetic recording apparatus. The aim of the invention is to expand the functionality of the device. Two counters 13, 14 and trigger 15 are connected in series, a clock pulse generator 16, the output of which is connected to the input of frequency divider 17, the output of the latter is connected to the second inputs of the first and second counters and the first input of the first key, the inverter whose output is connected with the second input of the first key and the first inputs of the second and third keys, the second inputs of which are connected respectively to the first output of the computer and the trigger output, the output of the first key is soy

Description

The invention relates to instrument engineering and can be used to record and reproduce discrete information from communication channels to a magnetic recording apparatus.

The aim of the invention is to expand the functionality by providing direct registration of information from a computer in a serial code.

FIG. 1 is a block diagram of the device; in fig. 2 is a diagram of the operation of the device.

The device for multi-channel recording and playback of digital information signals contains an error protection block 1 (BS), a converter 2 connected by an input and an output to the magnetic recording device 3, and in each channel the first register 4, the output of which is connected to the first input of the driver 5 pulses, two elements b and 7 delay, serially connected second register 8, decoder 9 and counter 10, trigger 11, element 12, serially connected second 13 and third 14 counters and second trigger 15, clock generator 16, output to second, connected to the input of the frequency divider 17, the first 18, the second 19, the third 20 keys, the inverter 21, the fourth 22, the fifth, and the sixth 24 keys.

The node 25, which contains two counters 13 and 14, a generator of 16 clock pulses, a divider 17, an inverter 21, and keys 18-20, 22-24, are designed to generate control signals for transmitting information from a computer.

The first and second outputs of block 1 are connected to the first and second inputs of the first register 4, the third output of block 1 is connected to the third input of the first register 4 and the second input of the pulse shaper 5, the first output of which is connected to the first input of the converter 2 through the first delay element 6, the second output of the driver 5 pulses directly connected to its second input. The second output of the latter is connected to the first input of the second register 8 and to the first input of the And 12 element. The third output of the converter 2 is connected via the second delay element 7 to the second input of the second register 8 and the second

the input of the counter 10. The output of the decoder 9 is also connected to the first input of the trigger 11. Two outputs of the counter 10 are connected respectively to the second input of the element 12, the output of which is connected to the third input

block 1,

Unit 1 is connected to the fourth, fifth, and sixth keys and to the adapter input data buses. The output of the frequency divider 17 is connected to the second inputs

the second and third counters and the first input of the first key, the second input of which and the first inputs of the second and third keys are connected via an inverter with the second inputs of the fourth, fifth and sixth keys and

the fourth output of the BSO 1. The second inputs of the second and third keys are connected respectively to the first (informational) output of the computer adapter and the output of the second trigger 15, the second input of which is connected to the output of the first counter 13, which input is connected to the second (control) output computer adapter. The outputs of the first, second and third keys are connected respectively to the clock, information and

control inputs of the first register, and the outputs of the first and third keys, in addition, are connected to the clock and control inputs of the computer adapter.

The device has two modes of operation:

recording-reproduction of information from a computer; recording-reproduction of information from communication channels through BSO 1.

Consider the first mode - recording-playback from a computer on the main channel. In this mode, the BSO 1 is de-energized and does not function. The signal from the fourth output of the BSO 1i Power supply The BSO has a zero level, which, entering the second inputs of keys 22-24, closes them and

through the inverter 21 opens the keys 18-20, through which the input of the register 4 can receive information signals from the computer, ticks and control signals providing

reception from a computer 48 (or 96) bit messages.

The generator 16 clock pulses gives the clock frequency to the input of the divider 17, which at its output forms clocks

frequency fi y- (see Fig. 2) and gives them to

the second inputs of counters 13 and 14, through the public key 18 and to the first input of the computer and to the third input of the register 4. These clocks of the device 25 synchronize the output information and control signals of the computer. If there is an information message in the computer (48 or 96 bits) that needs to be recorded on the magnetic recording apparatus, the computer at the first input of the counter 13 outputs a control signal, which starts the countdown of the 21-Ti time interval (see. Fig. 2) . At the end of this interval from the output of the counter 13, a signal is output to the counter 14 and to the second input of the trigger 15. At the output of the trigger 15, the control signal 14 is generated by the counter 14 with a positive level of 48 (or 96) Ti, which through the public key enters the second computer input and first register entry 4.

By this control signal, the computer issues a 48 (or 96) bit message, which through the public key 19 goes to the second input of register 4.

Consider the second mode - recording-playback of information from the BSO 1. In this mode, the BSO 1 is turned on, a positive signal is output from the fourth output of the BSO 1. The power supply of the BSW, which, acting on the second inputs of keys 22-24, opens them and the information on the first - the third inputs of register 4 are supplied only from BSO 1 via public keys 22-24. A positive signal, being fed to the input of inverter 21, closes the keys 18-20 and the recording of information from the computer is impossible.

The invention makes it possible to record digital information from a computer to a magnetic recording apparatus, which in this case is represented as an external computer storage device. The total amount of recorded information is determined by the number of magnetic tracks and the density of recording on them. For each magnetic track, one channel (one device 25) is required for recording-playback.

The invention is most expediently applied to computers operating in control complexes, where there are channels for transmitting information in a sequential code. In this case, information transmitted to the channels can be recorded and stored on the magnetic recording apparatus. which, after reproduction, can be used for calculations and analysis.

Claims (1)

The invention of the device for multi-channel recording 5 and reproducing the digital information signals by aut. St. No. 1059610, characterized in that, in order to expand the functionality by providing direct registration of information from a computer in a sequential code, additional two counters connected in series, an additional trigger, and an element NOT, six elements AND, a clock generator 5 pulses and a frequency divider, through which the output of the clock generator is connected to the second inputs of two additional counters and through the first I element to the third input of the first register of each recording / playback channel, the inputs of the third and first I elements are connected to the output of the additional trigger and the first output bus of the computer, respectively, while the second input of the additional trigger is connected to the output of the first additional counter, the input of which is connected to the second output bus of the computer, the first, second and three the third outputs of the error protection block are connected respectively to the first, second and third inputs of the first register through the fourth, fifth and sixth AND elements and directly to the corresponding input computer buses that control the output of the protection block 5 errors connected to the other inputs of the fourth, fifth and sixth elements And, and through the element NOT to the other inputs of the first, second and third elements And, and the outputs of the first and third elements And connected 0, respectively, to the clock and control input computer buses.