SU576586A1

SU576586A1 - Device for reproducing phase-modulated signals

Info

Publication number: SU576586A1
Application number: SU7602372363A
Authority: SU
Inventors: Альгимантас-Бернардас Антанович Килна
Original assignee: Институт Физики И Математики Ан Литовской Сср
Priority date: 1976-06-17
Filing date: 1976-06-17
Publication date: 1977-10-15

Description

1one

Изобретение относитс к области приборостроени .The invention relates to the field of instrumentation.

Известно устройство дл воспроизведени фазомодулированных сигналов (ФМС), содер}каш ,ее генератор опорной частоты, фазовый модул тор, схемы И, фильтры и фазовращатели 1. Устройство имеет сложную схему и недостаточно надежно в работе.A device for reproducing phase-modulated signals (FMS), porridge}, its reference frequency generator, phase modulator, AND circuits, filters and phase shifters 1 is known. The device has a complex circuit and is not reliable enough in operation.

Известное устройство аналогичного назначени 2 пе позвол ет осуществл ть выделение синхроимпульсов, вырабатываемых или своим генератором, или ранее записанных на магнитном носителе.The known device of the same purpose 2 does not allow the selection of clock pulses generated either by its generator or previously recorded on a magnetic medium.

Наиболее близким к изобретению по технической сущности вл етс устройство дл воепроизведени фазомодулированных сигналов, содержащее усилитель воспроизведени , подключенный через формирователь и схемы И к выходным щинам, триггер, св занный с вторыми входами схем И, схему ИЛИ, входы которой соединены с выходными шинами, последовательно соединенные генератор импульсов и первый счетчик, св занный с первым входом триггера, а также второй счетчик 3. Это устройство не обладает достаточно высокой помехоустойчивостью, что приводит к сбою записываемой и воспроизводимой информации .The closest to the invention in its technical essence is a device for phase-modulated signals, containing a reproduction amplifier connected through a driver and AND circuits to the output capacitors, a trigger connected to the second inputs of the AND circuits, the OR circuit, whose inputs are connected to the output buses, sequentially connected pulse generator and the first counter associated with the first trigger input, and the second counter 3. This device does not have sufficiently high noise immunity, which leads to failure recording and reproducing information.

Дл повыщени помехоустойчивости предлагаемого устройства оно снабн ено делителем частоты, включенным между выходом генератора импульсов и первым входом второго счетчика, блоком задержки, включенным между выходом схемы ИЛИ и вторым входом второго счетчика, последовательно соединенными регистром и блоком совпадени кодов, включенными между выходами первого и второго счетчиков, при этом выход блока совпадени кодов св зан с вторым входом триггера , а вход регистра - с выходом схемы ИЛИ.To increase the noise immunity of the proposed device, it is equipped with a frequency divider connected between the output of the pulse generator and the first input of the second counter, a delay unit connected between the output of the OR circuit and the second input of the second counter, sequentially connected by a register and a block of code matching between the outputs of the first and second counters, with the output of the code match block associated with the second trigger input, and the register input with the output of the OR circuit.

На чертеже показана структурна схема описываемого устройства.The drawing shows a block diagram of the described device.

К входу усилител воспроизведени 1 подключен входной залсим 2, а к выходу через формирователи 3 и схемы И 4 выходные щины 5. К вторым входам схем И подключен триггер 6, а к их выходам - схема ИЛИ 7. Между схемой ИЛИ и генератором импульсов 8 включен счетчик 9, а счетчик 10 подключен к делителю частоты 11 неносредственно и к блоку совпадени кодов 12 через регистр 13. К счетчику 10 присоединен блок задержки 14.The input amplifier 1 is connected to the input of the playback amplifier 1, and the trigger 6 is connected to the output through the drivers 3 and 4 output circuits 5. The second inputs of the AND schemes are connected to the trigger 6, and to their outputs an OR circuit 7. Between the OR circuit and the pulse generator 8 is on the counter 9, and the counter 10 is connected to the frequency divider 11 directly and to the block of coincidence of the codes 12 through the register 13. A delay block 14 is connected to the counter 10.

Claims

From the outputs of the formers 3, the AND 4 circuits receive impulses that carry information about the phase-modulated signal. These pulses are passed to the output buses only in the case of the presence at the inputs of the circuits AND of the resolving potential of the synchronization coming from the output of the trigger 6. The generation of the synchronization potential is terminated by counters 9 and 10, register 13 and block 12. Counter 10 counts the pulses from the generator 8 passed through divider 11. If the codes of counter 9 coincide with the register code, block 12 outputs a pulse, which translates trigger 6 into another state, thereby allowing the information signal to pass through AND 4 schemes. the presence of sufficiently noticeable changes in the reproduced signals, provided that the value of neighboring clock periods will not differ by more than ± 25%. Claims An apparatus for reproducing phase-modulated signals comprising a reproduction amplifier connected via drivers and AND circuits to output buses, a trigger connected to the second inputs of the AND circuits, an OR circuit whose inputs are connected to the output buses, serially connected impulse generator and the first counter associated with the first input of the trigger, as well as the second counter, characterized in that, in order to improve the noise immunity, it is equipped with a frequency divider, chalk-powered generator output and the pulses and the first input of the second counter, a delay unit connected between the output of the OR circuit and the second input of the second counter, are serially connected by a register and a code matching unit connected between the outputs of the first and second counters, while the output of the code matching unit is connected to the second trigger input, and the register input is with the output of the OR circuit. Sources of information taken into account in the examination 1. US patent No. 3287505, cl. 179-100.2, publ. 1966.

2. US patent number 3299414, cl. 340-174.1, publ. 1967.

3. The copyright certificate number 430434, cl. G 11B 5/06, 1972.

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