SU1683051A1 - Trainer for operators - Google Patents

Abstract

The invention relates to simulators for teaching equipment maintenance and is intended for use in electronic equipment for various purposes, including for testing hardware and software monitoring systems and equipment diagnostics. The purpose of the invention is to expand the didactic capabilities of the device. The essence consists in introducing into the device a second register 2, a block 4 of memory, elements AND 6, 7, a second generator 12 of pulses and an element OR 13, which makes it possible to imitate both steady and random failures on the equipment. By introducing the second element OR 18, the third counter 19 and the third decoder 20, an increase in the reliability of the results of the operation of the device is achieved. 1 il.

Description

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The invention relates to simulators for teaching equipment maintenance and is intended for use in electronic equipment for various purposes, including for testing hardware and software monitoring systems and equipment diagnostics.

The purpose of the invention is to expand the didactic capabilities of the device.

The drawing shows the functional diagram of the device.

The device contains registers 1 and 2, blocks 3 and 4 of memory, switching element 5, elements 6 and 7, address decoder 8, group 9 of elements 9, isolation elements 10, generators 11 and 12 pulses, element 13, element 14 delays, element 15, counter 16, decoder 17, element OR 18, counter 19, decoder 20, counter 21 (time), signaling node 22, fault generation outputs 23, response input node 24.

The device works as follows

The instructor enters the fault address code using the first register 1 in block 3, from the output of which the fault address code is fed to the input of the address decoder 8, at one of the outputs of which a signal arrives that arrives at the first input of the corresponding element A 9 of the group. Then the instructor selects the steady or random failures mode using register 2, which is stored in block 4. In the steady fail mode, the signal from the first output of block 4 is fed to the first input of the And 6 element, and in the random fail mode, the signal from the second output of block 4 is fed to the second input element is AND 1. After that, the instructor presses the button of element 5, a pulse signal from which enters the second inputs of elements AND 6 and 7 directly and through element 14 of the delay to the inputs of counter 21 (time), as well as to the input of element OR 18, s exit to orogo signal is supplied to the reset inputs of counters 16 and 19. Counter 21 starts counting time from the input fault in the equipment.

In the steady failure mode, the signal from the output of the element And 6 is fed to the input of the generator start 11 pulses. The pulses from the output of the generator 11 are fed to the input of the element OR 13, from the output of which the pulses go to the second inputs of elements AND 9 of the group, from one of the outputs of which through the element 10 and the output 23 of the formation of faults the pulses go to one of the interconnects of the equipment. These pulses are used as an interfering signal interfering with the normal functioning of the apparatus. In the operation of the apparatus failures are observed. Failures cannot be eliminated by mechanically replacing blocks of real equipment with spare ones. In this case, the student needs to localize the source of interference that prevents the normal functioning of the equipment, which requires him

0 all knowledge-skills and maintenance skills of the equipment, including the skills to use portable measuring devices. When a suspected circuit is detected, the operator commutes it using the node

5 24 with the second input element And 15 and the input of the counter 19. If the suspected circuit is defined incorrectly, then the pulses from node 24 do not coincide with the generator pulses coming from the output of the first element

0 OR 13 to the input of the first element AND 15, at the output of which there will be no pulses or will be in the event of an accidental coincidence, while the counter 19 counts the number of pulses until the output of the decoder

5 2O the signal arriving at the input of the element OR 18 is not shown, but from its output to the reset inputs of the counters 16 and 19. Thus, random pulses coming from the node 24 are eliminated if the

0 detected /; and suspected chain.

If the suspected circuit is defined correctly, then the pulses from the node 24 coincide with the pulses of the generator, and at the output of the first element I 15 there appear pulses

5, which counts the counter 16. At a certain output of the decoder 17, a signal appears, and the counter 16 counts the necessary number of pulses. Since the decoder 17 output corresponds to

0 fewer pulses than the decoder 20, then the signal at the output of the decoder 17 appears before the zeroing of the counters 16 and 19 occurs. This signal is fed to the input of the node 22

5 alarm, which signals the operator about the correct localization of the fault, The same signal stops the counter 21 and generators 11 and 12, Counter 21 records the time spent searching for faults, and as a result of stopping the generators, the interference with the normal operation of electronic equipment disappears.

5 To complicate the task, the instructor uses the random failure mode. The signal from the output element And 7 is fed to the input of the generator start 12 pulses. The generator 12 generates a pseudo-random sequence of pulses. Further

operation of the device is similar to the steady failure mode.

Claims (1)

Claims An apparatus for training operators, comprising a serially connected first register, a first memory block and a first decoder, the outputs of which are connected to the first inputs of a group of I elements, the outputs of which are connected to the inputs of the corresponding isolation elements, the outputs of which are outputs the formation of faults, the node input responses, the output of which is connected to the first input of the first element And, the output of which is connected to the counting input of the counter, the outputs of which are connected to the inputs of the second decoded Pa, the output of which is connected to the input of the alarm unit, the input of the stop of the first pulse generator and the control of the second counter input, the start and installation inputs of which are connected respectively to the outputs of the delay element and the switching element, the output of which is connected to the input of the delay element different that, in order to expand the didactic capabilities of the device, two OR elements are introduced into it, the second register, the memory block and the pulse generator, the second and third AND elements, the third decoder and counter, the count Its input is connected to the output of the response input node, and the outputs are connected to the inputs of the third decoder, the output of which is connected to the first input of the first OR element, the output of which is connected to the control inputs of the first and third counters, and the second input is connected to the output of the switching element and the first the inputs of the second and third elements are And, the second inputs of which are connected respectively to the outputs of the second memory block, and the outputs to the start inputs of the generators, pulses whose outputs are connected to the corresponding inputs torogo OR gate whose output is connected to second inputs of the first AND gate and the AND group, the second pulse generator stop input connected to the output of the second decoder, and the outputs of the second register are connected to respective inputs of the second block memory