SU1674370A1 - Displacement-to-digital converter - Google Patents

Abstract

The invention relates to the field of automation and computer technology and is intended for use in automatic displacement measurement systems. The aim of the invention is to increase the reliability of the information of the converter on the movement by introducing a delay in the issuance of information when it is changed. The goal is achieved by the fact that the first and second D-flip-flops, a multiplexer, a pulse generator, the first counter, the first and second current-limiting elements, the first, second, third, fourth optocouplers, the element EXCLUSIVE OR AND-NOT element, register, second counter. The introduction of additional elements in the displacement transducer to the code will automatically delay the release of information about the incident is moved to N cycles gating, for which there is a new assessment of the condition and issue an acknowledgment information change if the new condition remains unchanged for N ^times. T _strobe . 4 il.

Description

The invention relates to automation and computing and can be used in automatic displacement measurement systems.

The aim of the invention is to increase the reliability of the information of the converter on the movement by introducing a delay in the issuance of information when it is changed.

FIG. 1 and 2 a flowchart of the transducer to the code is presented; in fig. 3 and 4 - diagrams of output signals.

The displacement transducer to the code contains the displacement sensor 1, the first current-limiting element made in the form of a resistor 2, the first 3 and second 4 optocouplers, the first D-flip-flop 5. the second current-limiting element made in the form of a resistor 6, the third 7 and fourth 8 optocouplers, the second D-flip-flop 9, multiplexer 10, element EXCLUSIVE OR 11. element AND-NO 12, register 13, generator 14 pulses and counters 15 and 16

The displacement transducer to the code works as follows.

When the signals from sensor 1 are transferred from state 1 to state 2, optocoupler 3 is ignited and optocoupler 7 goes out, trigger 5 is reset, optocouplers 4 and 8, and trigger 9 remain in the same state (resistors 2 and 6 are used to limit the current through optocouplers). At the same time, the signal level at the output of a multiplexer 10 becomes high, and at the output b remains unchanged. At the exit

ABOUT

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element EXCLUSIVE OR 11 signal level becomes high, and the output element AND-NOT 12 - low (since the signal level at the output of the CR counter 15 is high). The states of the output of multiplexer 10, the output of element 12, the output of CR of counter 15 along the positive edge of a pulse from generator 14 are latched into register 13. Thus, in the next cycle, the increment of counter 15 is resolved until the states of the signals sin, sin are constant , cos, cos, or the signal at the output of the CR of the counter 15 does not go into a low state — this is a sign that the state of the 2 signals from the sensor is stable enough and you can already increment the counter 16 containing the code for the angle of rotation of the sensor. In the next cycle, the counter 15 is re-initialized, and the inputs a and b of the multiplexer 10 switch the inputs of cos and sfn signals, respectively. If the sensor signal states change before the low level at the CR output of the counter 15 is turned off, the counter in the counter 15 will stop and no change in the code of the angle of rotation of the sensor in the counter 16 will occur. The capacity of the counter 15 and the period of the clock frequency are chosen based on the maximum speed of the machine executive and the type of sensor so that the delay in changing the code of the measured angle of rotation of the sensor does not exceed 1/4 of the period of the sin and cos signals from the sensor. In this way, the reliability of information at the output of the device is achieved.

Similarly, the converter operates in the negative direction (changing the signal cos).

Let at the moment to (Fig. 3) at the inputs A and B of the multiplexer 10 be O, then the signal sin is switched to the output of a and the signal cos is output to the output b. The clock input of the register 13 receives a clock signal from the pulse generator 14, while at the DO input there is a low level and at the D2 input it is high. At the time ti, as a result of movement in the negative direction, the signal cos at the output b of the multiplexer 10 goes to a high state. The low level signal remains at the DO input of register 13, and the signal level at the D1 input is reversed.

The positive state of the clock signal overwrites the state of the inputs of the register 13 to its outputs. At time t2, the signal at output Q1 changes its state to the opposite, allowing the decrement operation of the counter 15. After eight cycles at time ta at the output CR

Counter 15 appears a carry signal that permits the counter to count 16. At time U, the first and second outputs of counter 16 change their states to opposite. At the same time, the signal cos is switched on the output a of the multiplexer 10, and sin on the output b. In the next cycle of operation, a low level signal appears at the output of Q2 register 13, which lasts one cycle and is overwritten into the counter 15 of a preselected seed number (in this case, 7).

The converter operates in such a way that in the steady state at outputs a and b

the multiplexer 10 is connected to those signals that are currently at a low level. With a simultaneous change in the signals sin and cos, the signals at the outputs a and b of multiplexer 10 are simultaneously switched to a high state and, therefore, the counting by counter 15 is prohibited.

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Claims (1)

Invention Formula The displacement transducer in the code containing the displacement sensor, the first and second D-triggers. D- and C-inputs of which are connected to a common bus, multiplexer, 0 the first and second control inputs of which are connected respectively to the first and second outputs of the first counter, the outputs of which are the outputs of the device, a pulse generator, different 5 by the fact that, in order to increase the reliability of the converter, two current-limiting elements, four optocouplers, an EXCLUSIVE OR element, an AND-NOT element, a register, a second counter, the first and 0 the second outputs of the displacement sensor, respectively, through the first and second current-limiting elements are connected to the first inputs of the first and second optrons, the second inputs of which are connected respectively to the third and fourth outputs of the displacement sensor and the first inputs of the third and fourth optocouplers, the second inputs of which are connected respectively to the first inputs of the first and second 0 optocouplers, the outputs of which are connected respectively to the R-inputs of the first and second D-triggers, the S-inputs of which are connected respectively to the outputs of the third and fourth optocouplers, the direct outputs of the first 5 and the second D-flip-flops are connected respectively to the first, second and third and fourth inputs of the multiplexer, the inverse outputs of the first and second D-flip-flops are connected respectively to the fifth, sixth and seventh and eighth inputs of the multiplexer, the first output of which is connected to the first input of the EXCLUSIVE element OR and the first information input of the register, the second output of the multiplexer is connected to the second input of the EXCLUSIVE OR element, the output of which is connected to the first input of the NAND element, the output of which is connected to the second information the register input, the clock input of which is connected to the clock inputs of the first and second counters and the generator output pulses, the register outputs are connected to the corresponding installation inputs of the second counter, the first and second outputs of which are connected respectively to the first and second installation inputs of the first counter, the second output of the NAND element is connected to the third information input of the register and connected to the first output of the second counter, the senior information the input of the second counter is connected to the common bus, and the younger ones - to the bus of the logical unit. -tHI.I -tni.1 -fa U -1nhl Fig 2 Consisting / fixing