SU1674153A1 - Device for graphic representation recognition - Google Patents

Abstract

The invention relates to the field of automation and measurement technology and is intended to recognize two-dimensional images of objects of arbitrary shape and determine their coordinates. The purpose of the invention is to improve the recognition accuracy and improve the accuracy of determining the coordinates of objects. The entered addressing unit, the buffer register unit, and the adaptive shift matrix make it possible to form an electronic aperture — a “window” of an arbitrary shape similar to a recognizable object. 6 Il.

Description

The invention relates to automation and measurement technology and is intended to recognize two-dimensional images of objects of arbitrary shape and determine their coordinates.

The aim of the invention is to improve the recognition accuracy and the accuracy of determining the position of a recognizable object.

FIG. 1 shows a block diagram of a recognition device; in fig. 2 is a block diagram of a quantization unit, a digital parallel correlator and an extremum extraction unit; in fig. 3 - block diagram of the addressing block; in fig. 4 is a block diagram of a dynamic memory block; in fig. 5 is a block diagram of an adaptive shear matrix; in fig. 6 - various forms of electronic window aperture.

The proposed device (Fig. 1) contains a television camera (TCE) 1. block addressing BA 2, block buffer registers BBR

3, a BEVE extremum extraction unit 4, a BC 5 quantization unit, a dynamic memory unit BST 6, an adaptive shift matrix AFM 7, a digital parallel correlator (CPC) 8.

The quantization unit 5 (Fig. 2a) contains an integrator 9, a delay line 10, a comparison circuit 11, the inputs of the integrator 9 and the delay lines 10 are combined and are the input of the block, and the outputs are connected to the inputs of the comparison circuit 11, the output of which is the output of the block .

The digital parallel correlator (Fig. 26) contains 256 elements EXCLUSIVE OR 12, the first shift register 13 at 256 bits, 256 elements OR-NOT 14, the second shift register 15 at 256 bits, the parallel adder 16. The first inputs of the elements EXCLUSIVE OR 12 vl The first 256-channel input of the CPC8 and the second inputs are connected to the outputs of the shift register 13, whose information input is the second input of the block

Vi j

ate

CJ

The device and the fourth input are simultaneously, and the clock input combined with the clock input of the shift register 15 is the third input of the block and the fifth input of the device at the same time. The information input of the shift register 15 is the fourth input of the block and the sixth input of the device simultaneously, and the outputs are connected to the first inputs of the OR-NOT 14 elements, the second inputs of which are connected to the outputs of the EXCLUSIVE OR elements 12, and the outputs are connected to the inputs of the parallel adder 16, the output of which is the output of the block.

The extremum extraction unit 4 (Fig. 2c) contains a comparison circuit 17, a counter 18 and two buffer registers 19.1 and 19.2. The clock input of the counter 18 is the second input of the block, and the output is connected to the information input of the buffer register 19.2, the output of which is the output of the block and the output of the device 1ЛВс simultaneously. The information input of the buffer register 19.1, combined with the first input of the comparison circuit 17, is the first input of the block, and the output is connected to the second input of the comparison circuit 17, the output of which is connected to the pins of the buffer registers 19.1 and 19.2.

Addressing unit 2 (FIG. 3) contains sixteen first counters 20, a second counter 21, sixteen multiplexers 22 and a pending multivibrator 23. The resolution inputs of counters 20 are combined with the installation input O of counter 21 and are the first input of the block, the clock inputs of all counters are combined with the input of the standby multivibrator 23 is the second input of the block, the inputs of the presetting of the counters 20 are the third 16-channel input of the block. The outputs of the counters 20 are connected to the first information inputs of the multiplexers 22, the second information inputs of which are combined and connected to the output of the estimator 21, and the control inputs are combined and connected to the output of the waiting multivibrator 23, which is simultaneously the second output of the block, and the outputs of the multiplexers 22 are 16 channel block outputs

The dynamic memory block 6 (FIG. 4) contains sixteen RAMs 24 and fifteen buffer triggers 25. The RAM 24 inputs and clock inputs of the triplers 25 are combined and are the second input of the block, the information input of the sixteenth RAM 24 is the first input of the block The address inputs of all the RAMs 24 are the third 16-channel input of the block. The outputs of the RAM 24 are a 16-channel block output,

at the same time, the output of each k-ro RAM 24 (except for the first) is connected to the information input of the k-th trigger 25, which is connected to the information input (k-1) of the first RAM 24.

The adaptive shift matrix 7 (Fig. 5) contains 256 multiplexers 26 and 256 D-flip-flops 27. The first information inputs of the multiplexers 26 of the first left column are the first 16-channel input of the block, and the first inputs of the multiplexers 26 of the other 6 columns are connected to inputs of D-flip-flops 27 (E-1) -x columns. Other information inputs of the multi-plexer 26 are connected to the outputs of certain D-flip-flops 27, the clock inputs of which are combined and are the second input of the block. The control inputs of all multiplexers 26 are combined and are

0 third input block. The outputs of all D-flip-flops 27 are the 256-channel output of the block.

t The block of buffer registers 3 contains seventeen 8-bit buffer registers. The clock inputs of all the registers are combined and are the third input of the block and device at the same time, the information inputs of the sixteen buffer registers are the first 16-channel input

0 of the block and the device at the same time, and the input of the seventeenth buffer register is the second input of the block. The outputs of the sixteen buffer registers are the first 16-channel input of the block, and the output of the seven-fifth register is the second output of the block.

The device works as follows.

First, reference information is loaded into the device, for example, from a computer. On

0 the input A of the device is given the binary codes of the initial personal addresses (LLA), the binary code of the window form is fed to the input B, a clocking pulse is fed to the input C, and the given write codes 5 are supplied to the RRB 3. Binary images are fed to the input D and E pattern and mask, 256 clock pulses are applied to input E. The reference is written to the first shift register 13,

0 and the mask is in the second shift register 15 CPK8.

After switching on the TV K 1, from its output G to the input G BA 2, lower quenching damping pulses begin to arrive, which at the beginning of each row sets the counters 20 to the ABO state, and the counter 21 to the O state. With the arrival of each clock pulse (TI ) coming from the output of n TCE 1 to the input of n BA 2, the waiting multivibrator 23 produces a negative pulse, during

the time of which multiplexers 22 commute to the output G BA 2 personal addresses from the counters 20. A clock pulse arriving at the input I of the BST 6 sets the RAM 24 to the read mode, while the reading is performed in accordance with the original address. When the pending multivibrator 23 returns to its original state, the read information is recorded along the pulse front in the D-flip-flops 27 of the first column of the AFM 7, while the information in the matrix also shifts to the right (window movement along the rows). Now at the output of BA 2, the address read from counter 21 is set for all the rows. The m-th column of the current image is read from RAM 24, which is written to buffer triggers 25 by slice of TI. increases by one). At the end of TI RAM 24 goes into recording mode and the information from each k-ro buffer trigger 25 is rewritten into (k-1) -e RAM 24. Thus, the window is shifted in the frame direction. Switching the counter 21 of the common address is performed on the TI front. .

The video signal y (n, t) from the output of TCE 1 is fed to the input of BC 5. In the integrator 9, the moving average y is calculated. At the output of the comparison circuit 11, a binary current image is formed in accordance with the expression

f3, if y (n, m) y 1, if y (n, m) y

Encoding block 5 can be implemented in both digital and analog form. The function of converting a video signal to a binary image may also be different. For example, in encoding, contours may be distinguished. It is important that the reference be coded in the same way.

From the output of BC 5, the current image is successively input to the BST 6, from the output of which the current image is already read by columns in the AFM 7. In the initial state, the AFM 7 consists of sixteen shift registers of sixteen bits each. When changing the code, the number of registers and their length can be changed by multiplexing the whole register or its part to the outputs of registers of other rows. A sample of the current image, generated in each clock cycle in AFM 7, is fed to the input to CPC 8, where the ordinate of the intercorrelation function is calculated in accordance with the expression:

R (n, m)

4g "with„ „

 2 2, t (n + k. M + Q f he M at M M

k

The MS output of the CPC 8 is the number R (n, m) arriving at the input of BEVE 4, the input L of which receives pulses from the output of the standby multivibrator 23 BA 2. The next number R (n, m) is compared by comparison circuit 17

l with the number stored in the first buffer register 19.1, in case the current value of the ordinate is greater than the stored one, then at the output of the comparison circuit 17 a signal is generated by which the current value of R (n, m) for | d is written to the first buffer register 19.1 . With the same signal, the contents of counter 18 are written to the second buffer register 19.2. Counter 18 counts the synchronous pulses TI, therefore it

Q low order bits determine the current element number m in a line, and high order bits determine the number n of the current line.

Thus, in BVE 4, the search for a global extremum of the mutual root of the relational function corresponding to the ideal of the standard and the object is performed, while its coordinates (pe, te) are fixed in the buffer register 19.2.

Claims (1)

Invention Formula An image recognition device comprising a television camera, the information output of which is connected to the information input of the dynamic memory block through a quantization unit, a parallel digital correlator, the output of which is connected to the information input of the extremum allocation unit, the output of which is to increase g, recognition accuracy and accuracy of determining the position of a recognizable object, it contains a block of buffer registers, an addressing block and an adaptive shift matrix, two information and clock From the inputs of the buffer register are the first, second, and third inputs of the device, the first output of the buffer register is connected to the information input of the addressing block whose output is connected to the information address input of the dynamic memory block whose clock input is connected to the first clock input of the block addressing and the first clock output of the television t-cameras, the second clock output of which is connected to the second clock input of the addressing unit, the clock output of which is connected to the clock input of the extremum recovery unit and the clock input of the adaptive shift matrix, the first information input of which is connected to the output of the dynamic memory block, and the second information input is connected with the second output of the buffer register block, the adaptive outputs of the digital parallel correlator inputs, the first and second information and clock inputs of which are respectively four fifth, fifth and sixth The active shear matrix is connected to 5 device inputs. Bjfj) 15 Stc 8sh1 21 25 ii S Zyh. 25 D P - M Figb