SU1672428A1 - Timer - Google Patents

Abstract

The invention relates to automation and computing and can be used in automated process control systems for issuing time codes to data processing systems based on requests from them. A distinctive feature of the timer is that it increases the reliability of the time code issued by eliminating the possibility of changing the time code issued at the time of receiving the time code. The aim of the invention is to increase reliability. To do this, a one-shot 2, a 3 frequency divider, an OR 5 element are introduced into the timer. 2 Il.

Description

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The invention relates to automation and computing and can be used in automated process control systems for issuing time codes to data processing systems based on requests from them.

The aim of the invention is to increase reliability.

FIG. 1 shows a functional timer scheme; in fig. 2 - time diagrams that show his work.

The timer contains a clock generator 1, a one-shot 2, a divider 3 frequencies, a counter 4, an element OR 5, a trigger 6 and a register 7, a group of 8 inputs of the initial time code, an input 9 of recording resolution, an input 10 of resolution reading and a group of 11 information outputs.

The one-shot 2 can be made in the form of the first and second D-flip-flops (integrated chip 564ТМ2). The C inputs of which are the input and control input of the one-shot 2, respectively. The output of the first D-flip-flop is connected to the D input of the second D-flip-flop, the output of which is connected to the R-input of the first D-flip-flop and the output of the one-shot 2. On the D-input of the first D -trigger set to high level. In addition, the one-shot 2 can be made as a single-shot (integrated chip 564A (1j, the trigger input on the leading edge of which is the input of one-shot 2. and a D-flip-flop (integrated chip 564ТМ2), the D-input of which is connected to the output of the one-shot. C The input and output of the D-flip-flop are the control input and the output of the one-shot 2, respectively.

The timer works as follows.

On group of information; i ;; The 1x inputs of the counter 4 receive the initial time code, and the input of the one-oscillator 2 receives the recording resolution pulse.

The pulses generated at the output of the clock generator 1 are fed to the control input of the one-oscillator 2. frequency divider input 3 and trigger synchronous input 6.

On the leading edge of the first pulse arriving at the control input of the odorovator 2 after the leading edge of the pulse arrives at its input, a pulse is formed at the output of the one-vibrator 2, the duration of which is a multiple of the period of the pulse signal received by its control input and fed to the input reset to the divider 3 frequency and the resolution of the recording entry counter 4.

On the leading edge of the pulse generated at the output of the one-shot 2, the initial time code entered at the inputs of the counter 4 is recorded in the counter 4

and enters the inputs of register 7. The read enable pulse is fed to input 10.

Using the 3 frequency divider, a pulsed signal is generated at the required frequency by recalculating

pulses generated at the output of the clock generator 1, in the interval between adjacent pulses formed at the output of the one-shot 2. On the leading edge of the corresponding pulse received at the input of the frequency divider 3, the output of the frequency divider 3 produces a pulse that is a multiple of the pulse period duration, enrolled at his entrance and enters at

counter input 4.

On the leading edge of the pulse formed at the output of the divider 3 frequency, in the absence of a pulse at the input of the recording resolution of the counter 4

4 is increased by one.

The pulses generated at the outputs of the one-shot 2 and the splitter 3 frequencies and the read resolution pulse, received at the input 10, through the element OR 5 enters

on the trigger information entry 6.

The trailing edge of the first pulse arriving at the synchronous input of the trigger b after the forward (trailing) edge of the pulse arrives at its information input.

At the output of trigger 6, a high (low) signal level is set.

On the trailing edge of each pulse received at the input of recording resolution register 7 from the output of trigger 6, the time code,

formed at the outputs of counter 4, is written to register 7 and fed to the outputs 11 of the timer.

The time frames (Fig. 2) show pulse signals: a - at the output

clock generator i. b at the input 9 of the device; in the output of the one-shot 2: g - at the output of the divider 3 frequencies, d - at the output of the low-order bit of counter 4; e - at the input 10 of the device: W - at the output of the element OR

five; h - at the output of the trigger 6; and at the exit of the lower bit of the register 7.

Claims (1)

Claims of the invention A timer comprising a counter, a clock generator, a register and a trigger, wherein the bit outputs of the counter are connected to the information inputs of the register, the outputs of which are informational outputs of the timer, characterized in that in order to increase the reliability. A one-shot vibrator, a frequency divider and an OR element are entered, the group of information inputs of the counter is a group of inputs of the initial timer time code, the first input of the single-vibrator is an input of recording resolution of the timer, the output of the one-vibrator is connected to the recording resolution enable input of O, frequency and with the first input of the element OR, the second input of which Outlet gen.1 Dx.9 & b1x.adno62 Out.de. J Out nr.p. Dx.10 IHT5 breathing tr. d Outlet reg. 7 It is connected to the output of the frequency divider and the counting input of the counter, the third input of the OR element is the input to enable the timer to read, the output of the element OR is dinen with informational entry of thrggger. the synchronous input of which is connected to the output of the clock generator by the second input of one vibrator and the information input of the frequency body, the output of the trigger is connected to register resolution enable input FIG. 2