SU1667245A1 - Scaling device - Google Patents

Abstract

The invention relates to the field of automation and can be used in various devices of relay automation with a large number of cycles of inclusions. The purpose of the invention is to increase reliability due to the uniformity of loading of electromagnetic relays by the number of operations. The decoder 4 and logic elements AND 3.1 ... 3.N, the number of which is equal to the number of bits of counter 1, are entered into the device, the outputs of the decoder 4, corresponding to different code combinations at its inputs, are connected to the first inputs of elements 3.1. 3 ... .N, the second inputs of which are combined and connected to the terminal of the counting input 5, the outputs of elements AND 3.1 ... 3.N are connected to the counting inputs of each trigger cell 2.1 ... 2.N, the high-order output of counter 1 is connected to the low-order bit, the inputs of the decoder 4 are connected to the additional outputs of each riggernoy cell 2.1 ... 2.N, and the output device 6 is one of the outputs of the decoder 4. The device has extended life operating time when compared with known scaler to electromagnetic relays and can be used in the apparatus with a large inclusions cycle during operation. 3 il.

Description

The invention relates to a pulse technique and can be used in various devices of relay automation with a large number of cycles of inclusions.

The aim of the invention is to increase reliability due to the uniformity of loading of electromagnetic relays by the number of operations.)

FIG. 1 shows a functional diagram of the device; in fig. 2 is a diagram of the element And 3; in fig. 3 - a decoder 4.

The device consists of a binary counter 1, which includes a series of sequentially connected trigger cells 2.1 - 2.N on electromagnetic relays, logic gates 3.1 3.1. 3.N, decoder 4, counting input 5 and output 6.

Elements 3.1 - 3.N are connected by their outputs to the inputs of the corresponding trigger cells 2.1 - 2.N. One input each element AND 3.1 - 3.N is connected to the corresponding output of the decoder 4. other inputs of all elements AND are combined and connected to the terminal of input 5. The output of the trigger 2.N of the most significant bit of counter 1 is connected to the input of the trigger 2.1 of the least significant bit. Decoder A is connected by its inputs to an additional output in each trigger cell 2.1-2.N containing information on the state in which the trigger is located (O or 1).

The output 6 of the device is a terminal connected to the last output of the decoder 4.

The device works as follows.

In the initial state, the counter 1 is reset to zero, from the first output of the decoder 4, the enable signal is sent to the input of the element 3.1. At all the other outputs of the decoder 4 there are no signals.

The decoder 4 contains the switching program in the circuit of the device after certain quantities of counting pulses are received at its input.

When the device is turned on, the counting pulses through the AND 3.1 element arrive at counter 1. After recalculating the Nth number of pulses, the trigger cells 2.1 - 2.N of the binary code set on the outputs of the trigger cells are decoded. In this case, the signal from the first output of the decoder 4 is removed, e appears at the second output. The passage of pulses through the element 3.1) stops. . The input pulses continue to arrive at the input of the trigger cell 2.2 of the counter 1 through the element 3.2.

From this point on, the trigger cell 2.2 becomes the younger one, and the trigger cell 2.1 becomes the highest-order counter 1.

Counter 1 continues to recalculate the input pulses,

After dialing the Nth number of pulses, the decoder 4 captures the new state of all bits of counter 1. The signal from the second output of the decoder 4 is removed and

appears at the third exit. As a result, the device circuit recombines again, the trigger cell 2.3 becomes younger, and the trigger cell 2.2 is the high-order counter 1.

Similarly, the process goes on. The cycle of operation of the device is completed at the moment it arrives at the input.

trigger cell 2.N of the last of the total number of pulses from input 5, equal to 2 (the capacity of the counter 1). The output signal is fed to the output 6 of the (N + 1) -th output of the decoder 4, which fixes the state of all bits of counter 1 at the moment of the arrival of the last pulse.

When programming the decoder 4, the table of changes in the state of counter 1 is used, taking into account the switching

in the device during its operation.

To evenly load the relay, the number of input pulses between switchings in counter 1

thirty

2N

P1 TUP with the number of bits N - 6, Hz 10 - 11, the program of the decoder 4 for the 6-bit counter 1 is shown in the table.

From consideration of the complete table of states of counter 1 for all 64 input pulses, it follows that the relays in the 1st and 3rd bits switch from O to 1 and from G to O 10 times, in the 2nd, 4th , The 5th and 6th bits from O are 11 times, and from 1 to O are 10 times.

FIG. 2 shows an example of the execution of the circuit of the AND 3 logic element and its connection to the trigger cell input; Element I 3 is made on the relay 7, which is one

the output of the winding is connected to the common bus input 5, and the other output - to the output of the decoder 4.

Normally closed contact 7.1 of relay 7 is included in the interdisc connection in series with contact 8.1, and normally open contact 7.2 is connected in parallel with another contact 8.2 of relay 9 in the previous discharge of counter 1. When a decoder 4 signal arrives at relay 7 constant voltage + EP it is triggered each time from negative pulses at input 5. The zeroing input through diode 10.3 (11.3) is connected to the relay coil 8.

The windings of the relay 8 are shunted by capacitors 12, in series with the windings are the isolating diodes 10.1, 10.2.

All subsequent trigger cells of the counter are made according to the scheme of the described cell. Thus, the second cell in FIG. 2 contains a relay 9 with contacts 9.1-9.4, diodes 11.1-11.3 and capacitors 13.1, 13.2.

The information about the status of the trigger cells is output to the decoder 4 from the normally closed contacts 8.1 (presence-absence in the voltage circuit - En).

FIG. 3 shows an example of the execution of the decoder 4, consisting of a matrix of diodes 14, a relay 15.1-15, N with self-blocking, separation diodes 16.1- 16.N and resistors 17.1- 17.N.

The discharge columns of the diode array are connected to normally closed contacts of the state control of trigger cells 2.1 -N.

Each row of the matrix is connected through a diode 16 to the corresponding output of the decoder 4 and the winding of the relay 15.2 - 15.N. The last row of the matrix is output 6 of the device,

The windings of the relay 15.1 are connected via diode 16.N + 1 to the device zeroing bus and the output of the decoder 4 connected to the first discharge element 3.1 of counter 1.

The second terminals of the windings of all relays are connected to a common power supply busbar - Ep.

The circuit elements related to each row of the decoder 4 are powered from the power supply bus + Ep through serially connected normally closed contacts 18.2-18.N of the relay of the next higher bits that are triggered in time later.

Diodes 14 in each row of the matrix are connected to those bit columns that correspond to 1 decrypted binary code (the pinout of the diodes in the scheme is shown conventionally).

The decoder 4 works as follows.

When a zero pulse is received, the relay 15.1 is activated and is blocked by its contacts 18.1. At the same time, a + UU signal is output to the 1st output of the decoder 4. All other relays are in the off state, because the control contacts of the state of the trigger cells are closed and all the columns of the matrix are

connected to the common power supply busbar -Ep, as a result of which the voltage on the anodes of the diodes 16 is not enough to operate the relay 15.2 - 15.N (voltage

equal to the voltage drop across the diode),

After the device starts up, when the counter 1 reaches the state set by the binary code in the first row of the decoder 4, the voltage -En is removed from all columns and the relay 152 through the resistor 17.1 and diode 16.1 receives the voltage from the power supply + UC bus.

Relay 15.2 operates, is blocked by its contacts and simultaneously opens its contacts 18.2 in the power supply circuit of relay 15.1.

Relay 15.1 turns off, and the signal from the first output of the decoder 4 is simultaneously removed.

Similarly, at the time of the signal on the next row of the matrix, the relay 15.3 is triggered, which by its contacts 18.3 turns off the relay 15.2. The signal from the second output of the decoder 4 is removed and appears at the third output, etc. The operation of the decoder 4 is terminated at the time of the signal on the last line, which serves as the output of the device.

Claims (1)

Invention Formula A scaling device containing successively connected trigger cells on electromagnetic relays, the counting buses of each of which are connected to the output bus of the previous trigger cell, the zeroing inputs of the trigger cells are combined and connected to the input of the initial installation of the scaling device, characterized in that increase of reliability due to the uniformity of loading of electromagnetic relays by the number of operations, a decoder and a group of logic elements I are entered into the device, the number of which is the number of trigger cells, the counting bus of the first trigger cell is connected to the output bus of the last trigger cell, the inputs of the decoder are connected to the additional outputs of the trigger cells, and the outputs of the decoder, except the last, are connected respectively to the first inputs of the I elements, the second inputs of which are connected to the counting input of the recalculation unit , outputs of elements AND connected to the counting buses of the respective trigger cells, and the last output of the decoder is the output of the device. Eni 64 imp. to the decoder pulses from the decoder of FIG. 2 to the decoder K1-F FIG. 3