SU1665383A1 - Device for message commutation - Google Patents

Abstract

The invention relates to computing and can be used in the construction of switching networks of multiprocessor computing systems. The aim of the invention is to increase productivity. The device contains a group of switching units 1. Switching unit 1 has information inputs and output 2, analog outputs 3, 4, combined with the help of resistors 5, output 6 and input 7 of the processor module, request input 8, confirmation output 9. 3 il.

Description

i

oh oh ate

CJ 00 CA

The invention relates to computing and can be used in the construction of switching networks of multiprocessor computing systems.

The aim of the invention is to increase the speed of the switching network. Figure 1 shows the functional diagram of the device; figure 2 is a functional diagram of the switching nodes; FIG. 3 shows an example of the execution of the input interfaces and will switch the emails.

The device (Fig. 1) contains a group of switching units 1 interconnected by informational inputs-outputs 2, each switching unit 1 contains the first and second analog outputs 3 and 4, the first analog outputs 3 of the switching units combining using resistors 5 between horizontal, and the second analog outputs 4 - vertically.

Switching unit 1 has output 6 and input 7 of the processor module, as well as input 8 of the request and output 9 of the confirmation.

Each switching unit 1 (figure 2) contains the first 10, second and third 11 input interfaces, switch 12, first 13, second and third 14 output buffer registers, first and second digital-to-analog converters 15, the outputs of which are connected to the inputs through the terminating resistors 16 analog circuit 17 comparison.

Each input interface 10, 11 (FIG. 3) contains a control block 18, an address decoder 19 and an input register 20. Switch 12 contains two arbitrators 21 output channels, four keys 22, two elements OR 23.

The device works as follows.

To describe the operation of the device, the following notation is entered: PQin - source request for information output (input 8); AQin - receiver acknowledgment of receipt of information (exit 9); PQa - a request to the arbitrator (from block 18); A0a - confirmation of the arbitrator (from block 21); PQout - request to write to the output register.

The data exchange between the processor modules associated with each switching node occurs when using packets moving in two directions: vertical and horizontal. The package consists of two parts: address and operational. The address part is the PM code, to whom the packet is addressed, and the operational part is the information itself. The packet from the output of the buffer register 14 of the adjacent node enters the input

The interface is activated, and the PQin line and output 9 are activated. The control block 18, according to the transition diagram, records in the input register gr 20. Next, the address is decoded and a request is made to one of the output channel arbitrators 21 (vertical, horizontal or PM channel). If the address part of the packet matches the code of the current block 1, then a request is made to the arbiter of the PM channel. Each output channel has its own arbiter 21. The arbitrator 21 accepts requests from the input interfaces and, depending on the priority of requests (priority of requests

5 records in the ROM on which the arbitrator is executed) gives confirmation to the corresponding input interface, this opens the corresponding key 22 and information from the output of the channel register 20, to which confirmation is given, is fed to the input of the output register 14 (13) sets the PQout signal, which, through the OR element 23, records the packet to the corresponding output

5 register 14. The OR element 23 combines PQout requests from the input interfaces 11 (10). The PM address uniquely determines the position of the PM in the matrix, i.e. vertical number (string) and horizontal number

0 (column). If the address part of the packet does not match the address of the node where the packet is processed along one coordinate (i.e., row or column), then an output channel is requested, which does not occur

5 matches. For example, if the column does not match, then a horizontal output channel is queried and the packet moves along the line until the column matches. If there is no match for either the column or the row, then

0, a channel is selected depending on the output signals of the comparison circuit 17. The comparison circuit 17 compares the load of directions vertically and horizontally and, therefore, the route will be chosen

5 in the direction with a smaller load. Such a construction of a switching node is known and it is implemented in a known device, in which a channel selection algorithm is also implemented based on the load of neighboring buffers. Such routing control is local. It requires low hardware costs, but is implemented on the basis of information about the load of neighboring nodes, which does not reflect the situation in the entire network (i.e., the entire direction). In this case, such situations are possible, when in one direction the buffer of the nearest node is empty and the other buffers are filled, at the same time the nearest buffer is in the other direction of the filling, and the others are empty in the same direction. In this case, the first direction with a larger total length is selected. which in turn will increase the package delivery time. It is proposed to control routing not to use local buffer loading information, but from some zone, which may be significant and which more adequately reflects the situation in the network along the directions. It is proposed to obtain this integral information using the following analog processing.

A code is converted that characterizes the loading of buffers into an analog signal using digital-to-analog converters 15.

The outputs of the digital-to-analog converters 15 together with the terminating resistors 16 form the analog outputs of the switching units.

The analog outputs of the switching units of the same name are interconnected by means of resistors 5 in directions, thereby forming a single electrical circuit. The voltage at each node of the network U is defined by the following expression:

U Z1 And + ... + Znin,

where z - idling transmission resistances;

I is the current of the transformed source;

n - the number of sources of the chain.

In device I, the current generated by each ADC 14, an, is the number of nodes in the direction. The transfer resistances characterize the contribution of each source to the resulting node voltage. For small dimensions of the network, resistors 5 can be neglected and replaced by conductors. In this case, a common line is obtained to which outputs 3 (4) are connected. The contribution of each source to the total voltage on the line is the same and it can be seen that the voltage in the line is proportional to the sum of the currents of all sources. This information is integral and more adequately reflects the network situation.

A comparison is made in the analog form of workload directions and the choice of less loaded.

A device built on these principles makes it possible to more adequately determine the less loaded direction and implement routing.

In the case of a large network dimension, in order to compensate for the resistance of the communication circuits (due to different physical interposition of the nodes) and to select the optimal control for different types of network load, resistances are introduced 5.

In this case, ladder type electrical circuits are formed in which the contribution of sources to the voltage at a particular node is different. The farther the source (in the signal

5), the smaller its contribution, and with increasing distance this contribution can be neglected. By varying the ratio of resistors 5, it is possible to choose the size of the zone with which the influence of sources is taken into account. As this ratio increases, the zone sizes decrease.

Claims (1)

Invention Formula 15 A device for switching messages containing a group of switching units, each switching unit containing first, second and third input interfaces, a switch, a first, second and third 0 output buffer registers, the first input of the first input interface of the switching unit is connected to the output of the processor module of the switching unit, the first inputs of the second and third input interfaces of the switching unit are information inputs of the switching unit, the information outputs of all input interfaces of the switching unit are connected to the inputs of the switching unit switch , 0 and the switch outputs are connected to the inputs of the first, second and third output buffer registers of the switching unit, the output of the first output buffer register of the switching unit is connected to the input of the switching module processor module, the first outputs of the second and third output buffer registers of the switching unit are information outputs of the switching unit , the second inputs of all input interfaces of the switching unit are connected to the request inputs of the switching unit, the outputs confirming all the input interfaces of the switching unit with They are connected to the switching unit confirmation outputs, so that, in order to improve performance, the first and second digital-analogue converters, whose inputs are connected to the load outputs of the second and the third output buffer registers of the switching unit, and the outputs of the first and second digital-to-analog converters of the switching unit are the first and second analog outputs 5 of the switching unit and connected to the first and second inputs of the analog comparison circuit of the switching unit; the output of the analog comparison circuit of the switching unit is connected to the address inputs of all the input interfaces of the switching unit; In the device, the first and second analog outputs with the analog outputs of the same name are the turns of the switching units of the group connected via matching resistors. FIG. 2 Fia.Z