SU1663609A1 - Multifunctional uniform structure cell - Google Patents

Abstract

The invention relates to automation and digital computing and can be used in constructing decision fields for associative parallel data processors. The aim of the invention is to enhance the functionality of a homogeneous environment cell by performing logical AND, OR, NOT operations on input variables, as well as switching input variables or the results of their logical transformation to any of the cell outputs. The cell contains four information inputs 1 - 4, four outputs 5 - 8, four tuning inputs 9 - 12, twenty elements AND 13 - 32, four controllable logic elements 33 - 36, four multiplexers 37 - 40 and two shift registers 41 and 42 In a homogeneous structure, split, group permutation, shift, merge, simultaneous partition and permutation operations are performed, logical operations, Boolean functions, and data switching are performed. 6 ill., 2 tab.

Description

The invention relates to automation and computing and is intended to build homogeneous computing structures.

The aim of the invention is to enhance the functionality of a homogeneous structure cell by performing logical AND, OR, NOT operations on input variables, as well as switching input variables or the results of their logical transformation to any of the cell outputs.

FIG. 1 shows a flowchart diagram; in fig. 2 is a functional diagram of a controlled logic element; Fig. 3 is a graphical interpretation of the functionality of a cell; in fig. 4 shows an example of building a switching circuit; in fig. 5 shows an example of performing a shift operation; in fig. 6 shows an example of constructing a function calculation scheme in a homogeneous structure.

The cell (Fig 1) contains four information inputs 1–4, four outputs 5–8, four tuning inputs 9–12, twenty elements AND 13–32, four controllable logic elements (ULE) 33–36, four multiplexers 37–40 and two shift registers .41 and 42

The controllable logical element (Fig. 2) contains three elements AND 43-45, three elements OR 46-48, element NOT 49 and multiplexer 50.

The cell operates as follows.

Cell Setup

Os O CO

ABOUT

oh oh

This mode of operation of the homogeneous structure is to ensure that the cells are configured to perform the required functions by writing control words to the shift registers 41 and 42 of the cells. As a result, control signals qi-qa ULE 33-36 and control inputs a and ai of multiplexers 37-40 cells of a uniform structure form control signals that commute input data streams in corresponding combinations to outputs 5-8 cells.

The operations performed by the data in the ULE and the output multiplexers, depending on the combination of control signals, are given respectively in Table. 1 and 2.

The writing of the control words in the shift registers 41 and 42 of the cells of a uniform structure is performed as follows.

The control inputs of 12 cells of a uniform structure are given a signal Z4 0. As a result, at the outputs of the elements AND 13-32 cells, control signals are formed: qi qa - Q3 "1 ai 0. Thus, in each cell of a homogeneous structure, the following operations are performed on the data :

Yi Xi;

 .Y2 X2;

Y3 X3; Y4 X ",

at the same time, information from information input 1 (Xi) in each cell enters informational inputs of shift registers 41 and 42, which allows for a bit-wise recording of required control words to shift registers 41 and 42 as follows. A binary word is applied to a group of inputs of a homogeneous structure.

And ai, n °, 32,11 °, az.p

oo

...,

where ac is the zero-bit value of the twelve-bit control word for the ULE (I,) –th cell. Then, the first setup input 9 of each cell is supplied with a write signal Zi 1, which is fed to the recording control inputs of the shift registers 41 of all n-column cells, which ensures the data from the information inputs of 1 cells are written to the zero discharge of the shift resistor 41. Next, a group of inputs homogeneous structure is given a binary word

In bl.n °, D2.n °, Ls.GL .., bm, n °,

where bij is the value of the zero bit of the control word for multiplexers 37-40 (i, jj-th cell.

When applying to the second setup input

The 10 cells of the recording signal Zz 1 in the shift registers of the 42 cells will be assigned the corresponding bits of the word B °, after which a pulse signal 2 will be sent to the third configuration input 11 of the homogeneous structure.

1, which is fed to the shift control inputs of the shift registers 41 and 42. As a result, the information recorded in these registers is shifted by one bit. Similarly, writing to

The shift registers 41 and 42 of the n-column cells of the following control word bits:

aij1, bij1, aij2, bij2, aij3aij11, bij11.

The functionality of the cell as a switching element allows

perform data conversion operations. The peculiarity of these operations is that, as a result of the transformations, the values of the elements of the processed operands do not change. Only the structural (positional) organization of operand elements is changed.

Thus, when performing operations of this type in accordance with the functionality of a cell on

the tuning inputs of ULE 33-36 cells need to send signals qi Q2 Q3 0. As a result, signals will be generated at the outputs Fi-F4 ULE 33-36 of all cells of the structure:

Fi Xi; F2 X2; Ps Xs;

F4 X4.

Thus, depending on the signals "1," 2 i coming from the corresponding outputs of the shift register 42 through the elements AND 25-32 to the configuration inputs

multiplexers 37-40, in the cell various data switching operations from the ULE 33-36 outputs to outputs 5-8 cells will be implemented.

Possible options for switching data from information inputs 1-4 to outputs 5-8 cells, provided that the control signals to the configuration inputs of multiplexers 37-40 are identical, are shown in FIG. 3. Among the operations of data switching, we can distinguish three classes of operations: binary merge, splitting, and group permutation. These operations are performed in a homogeneous structure as follows.

Binary fusion.

The problem solved by the device in this case is to form on the output group a homogeneous structure of the binary p-bit vector D, whose elements are the elements of the vectors

A XL X2Xk and B Yi, Y2Ys, and

p 2 max (k, s), and the structure D has the form

D Xi, Yi, X2, Y2Xk, Ys,

with k s.

D Xi, Yi, X2, Y2XiYs, Xi + 1, 0Xk,

0,

at k s,

D XL Yi, Xa, Y2Xk, YJ, 0, Yi + i0,

Ys

with k s.

After the formation of the switching circuit for performing operations, it is sufficient to supply the corresponding values of the first vector (A) and the second vector (B) to the corresponding inputs of the homogeneous structure groups.

An example of organization in the homogeneous structure of the switching circuit with A Xi, Xa Xs X4 and B Yi Ya Y3 UA when performing the operation of a binary merger is shown in FIG. four.

Splitting.

The problem solved by the device when performing operations of this type is to form a homogeneous binary structure on orthogonal output groups.

vectors,) 2Xk and B Yi, YaYs,

elements of which are elements of vector D.

The partitioning operation is similar to the previous one.

Group permutation.

The task solved by the device when performing this type of operation is to form at the outputs a homogeneous structure of the binary vector D, whose elements are the elements of the vector D, and the positional arrangement of the elements is different from their positional arrangement in D. These operations are performed similarly to the previous ones: for in the implementation, it is required to set in a homogeneous structure the corresponding circuit switching of information channels.

Among group permutation operations, shear operations are widely used. An example of the implementation of such operations in a homogeneous structure is shown in FIG. 5, where the switching circuit of information channels is graphically shown by the corresponding setting of the cells of a homogeneous structure. Xs X4 Xs Xe XL which is the result of a cyclic shift by one bit of vector A,

Cell Functionality

allow to realize in a homogeneous structure the compound operations of transformation of data structures, i.e. perform binary merge, splitting, and group permutation operations in the complex.

Cell functionality

as a logical element, they provide the implementation of logical multiplication, addition, and inversion operations on the data arriving at its information inputs 1-4.

Logical addition, multiplication and inversion of binary vectors.

The problem solved in the device is to form at the outputs a homogeneous structure of the binary vector D, which is the result of the logical addition (multiplication, inversion) of the vectors A and B entering the structure.

To perform these operations, it is sufficient to configure the diagonal cells of a homogeneous structure to perform the corresponding logical operation and set the required switching of information channels in a homogeneous

structure.

In the structure, it is possible to simultaneously perform two different logical operations.

Using structure resources to perform switching operations at the same time as logical processing, binary merge, splitting, and group permutation operations are also possible. The latter allows to form at the outputs

structure vector-result with the desired structural organization.

Calculation of Boolean functions of K-variables.

The task solved in the device is to form at one of the outputs of the structure the value of a Boolean function, the variables of which arrive at the information inputs of the structure.

To perform this operation in a homogeneous structure, it is necessary to preliminarily form an algorithm for calculating the function by setting the corresponding logical and switching functions of the cells. On infromatsmonnye structure inputs

serves the values of the variables.

An example of construction in a homogeneous structure of a function calculation scheme

Q (Xi vX2) fc (XiX4 v zX5) Y6 is shown in FIG. 6

Claims (1)

Invention Formula A multifunctional cell of a homogeneous structure containing the first and second multiplexers, the first and second elements AND, the output of the first multiplexer being connected to the output of the cell, characterized in that, in order to extend the functionality by performing logical operations AND, OR, NOT over the input variables as well as switching input variables or the results of their logical transformation to any of the cell outputs, it contains the third and fourth multiplexers, from the third to the twentieth And elements, four controls logical element and two shift registers, the first information inputs of the 1st controlled logical element are connected to the i-th information input of the cell, the information inputs of the shift registers are connected to the first information input of the cell and the i-th input of the 1st controlled logic element (1 1, 4), the first and second tuning inputs of the cell are connected to the recording resolution input of the first and second shift registers, respectively, the shift resolution input of which is connected to the third tuning input of the cell, even The vertically tuned input of which is connected to the first input of the k-ro element I (k 1, 20), the second input of the t-th element I is connected to the mth output (t 1, 12) of the first shift register, the t-th configuration input (t 1,3) The i-ro of the controlled logic element is connected to the (3- (3-t)) -th element AND, the 1st information input of the cell is connected to the i-th input of the first controlled logic element, the second information input of the cell is connected with the second information inputs of the third and fourth controlled logic elements, the third informational input of the last one with Connected with the third information input of the second controlled logic element and the third information input of the cell, the fourth information input of which is connected to the fourth information input of the second and third controlled logic elements, the output of the i-ro controlled logic element is connected to the 1st information inputs multiplexers from the first to the fourth, the output (t + 1) -ro of which is connected to (t + 1) -M outputs of the cell, the s-th input of the second shift register is connected to the second inputs (s + 12) -ro of the element I ( s 1, 8), (M) th tuning the input of the 1st multiplexer is connected to the output 12 + (2i - (2 -1 - 1)) - element I, Table 1 table 2 (if 30 (jfl) 20fa) fo- (xt) Figure 2 "V fa) №J hg Fig.Z h% 4 IG, " a 609G991 €